EVAL-ADM1275EBZ Datasheet, PDF (1/48 Pages) Analog Devices – Hot-Swap Controller and Digital Power

Data Sheet
Hot-Swap Controller and Digital Power
Monitor with PMBus Interface
ADM1275
FEATURES
Controls supply voltages from 2 V to 20 V
370 ns response time to short circuit
Resistor-programmable 5 mV to 25 mV current limit
±1% accurate, 12-bit ADC for current, VIN/VOUT readback
Charge-pumped gate drive for multiple external N-channel FETs
High gate drive voltage to ensure lowest RDSON
Foldback for tighter FET SOA protection
Automatic retry or latch-off on current fault
Programmable current limit timer for SOA
Programmable, multifunction GPOs
Power-good status output
Analog UV and OV protection
ENABLE pin (ADM1275-3 only)
Peak detect registers for current and voltage
PMBus fast mode compliant interface
16-lead QSOP and 20-lead QSOP and LFCSP
APPLICATIONS
Power monitoring and control/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers
GENERAL DESCRIPTION
The ADM1275 is a hot-swap controller that allows a circuit board
to be removed from or inserted into a live backplane. It also features
current and voltage readback via an integrated 12-bit analog-to-
digital converter (ADC), accessed using a PMBus™ interface.
The load current is measured using an internal current sense
amplifier that measures the voltage across a sense resistor in
the power path via the SENSE+ and SENSE− pins. A default
limit of 20 mV is set, but this limit can be adjusted, if required,
using a resistor divider network from the internal reference
voltage to the ISET pin.
The ADM1275 limits the current through the sense resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage—and, therefore,
the load current—is maintained below the preset maximum. The
ADM1275 protects the external FET by limiting the time that the
FET remains on while the current is at its maximum value. This
current limit time is set by the choice of capacitor connected to
the TIMER pin. In addition, a foldback resistor network can be
used to actively lower the current limit as the voltage across the
FET is increased. This helps to maintain constant power in the
FET and allows the safe operating area (SOA) to be adhered to
in an effective manner.
Rev. D
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APPLICATIONS DIAGRAM
2V TO 20V
R_SENSE
Q₁
2.95V
SENSE+
SENSE–
TO
20V VCC
+×50–
ADM1275-1
VCAP _LDO
UV
+
1.0V _–
OV
–
1.0V ₊
ISET
REF
SELECT
1.0V
SS
IOUT
+
–
CHARGE
PUMP
V_CP
GATE
DRIVE/
LOGIC
TIMEOUT
CURRENT
LIMIT _TIMER
ON
GATE
VOUT
CURRENT
LIMIT
CONTROL
V_CBOS
TIMER
TIMER
ON
TIMER
TIMEOUT
SENSE+
VOUT
IOUT
12-BIT
ADC
LOGIC
AND
PMBus
FLB
PWRGD
GPO1/ALERT1/CONV
GPO2/ALERT2
LATCH
SCL
SDA
ADR
GND
Figure 1.
In case of a short-circuit event, a fast internal overcurrent detec-
tor responds within 370 ns and signals the gate to shut down. A
1500 mA pull-down device ensures a fast FET response. The
ADM1275 features overvoltage and undervoltage protection,
programmed using external resistor dividers on the UV and OV
pins. A PWRGD signal can be used to detect when the output
supply is valid, using the FLB pin to monitor the output. GPO
pins can be configured as various output signals that can be
asserted when a programmed current or voltage level is reached.
The 12-bit ADC can measure the current in the sense resistor,
as well as the supply voltage on the SENSE+ pin or the output
voltage. A PMBus interface allows a controller to read current
and voltage data from the ADC. Measurements can be initiated
by a PMBus command. Alternatively, the ADC can run continu-
ously, and the user can read the latest conversion data whenever
required. Up to four unique PMBus addresses can be selected,
depending on the way that the ADR pin is connected.
The ADM1275-1 and ADM1275-3 are available in a 20-lead QSOP
and 20-lead LFCSP and have a LATCH pin that can be configured
for automatic retry or latch-off when an overcurrent fault occurs.
The ADM1275-2 is available in a 16-lead QSOP with latch-off
mode only.
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