EVAL-ADM1275EBZ Datasheet, PDF (12/48 Pages) Analog Devices – Hot-Swap Controller and Digital Power

ADM1275
Data Sheet
VCC 1
20 SENSE+
UV 2
19 SENSE–
OV 3
18 GATE
VCAP 4
17 GND
ISET 5 ADM1275-3 16 VOUT
TOP VIEW
SS 6 (Not to Scale) 15 FLB
TIMER 7
14 PWRGD
LATCH 8
13 SCL
ADR 9
12 SDA
ENABLE 10
11 GPO2/ALERT2
Figure 6. ADM1275-3 Pin Configuration, QSOP
OV 1
VCAP 2
ISET 3
SS 4
TIMER 5
PIN 1
INDICATOR
ADM1275-3
TOP VIEW
(Not to Scale)
15 GND
14 VOUT
13 FLB
12 PWRGD
11 SCL
NOTES
1. SOLDER THE EXPOSED PADDLE TO
THE BOARD TO IMPROVE THERMAL
DISSIPATION. THE EXPOSED PADDLE
CAN BE CONNECTED TO GROUND.
Figure 7. ADM1275-3 Pin Configuration, LFCSP
Table 7. ADM1275-3 Pin Function Descriptions
Pin No.
QSOP LFCSP Mnemonic
Description
1
19
VCC
Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low
supply voltage is detected. GATE is held low when the supply is below UVLO. During normal
operation, this pin should remain greater than or equal to SENSE+ to ensure that specifications are
adhered to. No sequencing is required.
2
20
UV
Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an
internal comparator to detect whether the supply is under the UV limit.
3
1
OV
Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an
internal comparator to detect whether the supply is above the OV limit.
4
2
VCAP
Internal Regulated Supply. A capacitor with a value of 1 μF or greater should be placed on this pin
to maintain good accuracy. This pin can be used as a reference to program the ISET pin voltage.
5
3
ISET
This pin allows the current limit threshold to be programmed. The default limit is set when this pin
is connected directly to VCAP. To achieve a user-defined sense voltage, the current limit can be
adjusted using a resistor divider from VCAP. An external reference can also be used.
6
4
SS
Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the
SS pin controls the current sense voltage limit, which controls the inrush current profile.
7
5
TIMER
Timer Pin. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The GATE
pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold.
8
6
LATCH
Signals that the device is latching off after an overcurrent fault. The device can be configured for
automatic retry after latch-off by connecting this pin directly back to the UV pin.
9
7
ADR
PMBus Address Pin. This pin can be tied to GND, tied to VCAP, left floating, or tied low through a
resistor to set four different PMBus addresses (see the Device Addressing section).
10
8
ENABLE
Digital Logic Input. This input must be high to allow the ADM1275-3 hot-swap controller to begin a
power-up sequence. If this pin is held low, the ADM1275-3 is prevented from powering up. There is
no internal pull-up on this pin.
11
9
GPO2/ALERT2
General-Purpose Digital Output (GPO2).
Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or
warning conditions are detected.
At power-up, this pin indicates the FET health mode by default. There is no internal pull-up on this pin.
12
10
SDA
Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up.
13
11
SCL
Serial Clock Pin. Open-drain input. Requires an external resistive pull-up.
14
12
PWRGD
Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on the
voltage present on the FLB pin.
15
13
FLB
Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback is
used to reduce the current limit when the source voltage drops. The foldback feature ensures that
the power through the FET is not increased beyond the SOA limits.
Rev. D | Page 12 of 48