EVAL-ADM1275EBZ Datasheet, PDF (11/48 Pages) Analog Devices – Hot-Swap Controller and Digital Power

Data Sheet
ADM1275
VCC 1
16 SENSE+
UV 2
15 SENSE–
VCAP 3
14 GATE
ISET 4 _ADM1275-2 13 GND
SS 5
TOP VIEW
(Not to Scale)
12 FLB
TIMER 6
11 PWRGD
ADR 7
10 SCL
GPO1/ALERT1/CONV 8
9 SDA
Figure 5. ADM1275-2 Pin Configuration
Table 6. ADM1275-2 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCC
Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low
supply voltage is detected. GATE is held low when the supply is below UVLO. During normal
operation, this pin should remain greater than or equal to SENSE+ to ensure that specifications
are adhered to. No sequencing is required.
2
UV
Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow
an internal comparator to detect whether the supply is under the UV limit.
3
VCAP
Internal Regulated Supply. A capacitor with a value of 1 μF or greater should be placed on this pin
to maintain good accuracy. This pin can be used as a reference to program the ISET pin voltage.
4
ISET
This pin allows the current limit threshold to be programmed. The default limit is set when this
pin is connected directly to VCAP. To achieve a user-defined sense voltage, the current limit can
be adjusted using a resistor divider from VCAP. An external reference can also be used.
5
SS
Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the
SS pin controls the current sense voltage limit, which controls the inrush current profile.
6
TIMER
Timer Pin. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The
GATE pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold.
7
ADR
PMBus Address Pin. This pin can be tied to GND, tied to VCAP, left floating, or tied low through a
resistor to set four different PMBus addresses (see the Device Addressing section).
8
GPO1/ALERT1/CONV General-Purpose Digital Output (GPO1).
Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or
warning conditions are detected.
Conversion (CONV). This pin can be used as an input signal to control when a power monitor
ADC sampling cycle begins.
At power-up, this pin defaults to a high impedance state. There is no internal pull-up on this pin.
9
SDA
Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up.
10
SCL
Serial Clock Pin. Open-drain input. Requires an external resistive pull-up.
11
PWRGD
Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on
the voltage present on the FLB pin.
12
FLB
Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback
is used to reduce the current limit when the source voltage drops. The foldback feature ensures
that the power through the FET is not increased beyond the SOA limits.
13
GND
Chip Ground Pin.
14
GATE
Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is
driven by the FET drive controller, which uses a charge pump to provide a pull-up current to
charge the FET gate pin. The FET drive controller regulates to a maximum load current by
regulating the GATE pin. GATE is held low when the supply is below UVLO.
15
SENSE−
Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin
sets the analog current limit. The hot-swap operation of the ADM1275 controls the external FET
gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin.
16
SENSE+
Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor
between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot-swap operation
of the ADM1275 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−).
This pin is also used to measure the supply input voltage using the ADC.
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