COREFIR-XX Datasheet, PDF (9/14 Pages) Actel Corporation – CoreFIR Finite Impulse Response (FIR) Filter Generator

CoreFIR
An example of the split lookup table implementation of
a FIR with eight taps (ntaps = 8) and four bits for inputs
(nbits_in = 4) is shown in Figure 4. In the example, eight
taps have been split into two groups. Each has four taps,
and each group addresses separate lookup tables. This
differs from the case in Figure 1 on page 4, which only
has one LUT.
x[n][3] x[n][2] x[n][1] x[n][0]
x[n-1][3] x[n-1][2] x[n-1][1] x[n-1][0]
x[n-2][3] x[n-2][2] x[n-2][1] x[n-2][0]
x[n-3][3] x[n-3][2] x[n-3][1] x[n-3][0]
x[n-4][3] x[n-4][2] x[n-4][1] x[n-4][0]
x[n-5][3] x[n-5][2] x[n-5][1] x[n-5][0]
x[n-6][3] x[n-6][2] x[n-6][1] x[n-6][0]
x[n-7][3] x[n-7][2] x[n-7][1] x[n-7][0]
Flow Control
Lookup Table
Lookup Table
Shifter
Shifter
Adder
Reg
Adder
Reg
Adder
Figure 4 • Example of Split Lookup Table Implementation
Output
Folding
The system clock rate of many FIR filter systems is a
multiple of the data rate (or data sampling rate). For
typical FPGA implementation, the size of the design is
key for efficient implementation. Thus, exploitation of
the ratio between the system clock rate and data rate is
an effective approach to reduce the size of the design. In
other words, folding or serialization of the computation
can reduce the size of the design. The DA algorithm for
FIR introduces bit-serialization of the operations. This
property of the DA can be very efficient for exploring the
ratio between system clock rate and data rate. If the
number of bits of input is nbits_in, it takes nbits_in table
lookup and additions to finish one output point of the
FIR. If the system clock rate is nbits_in times faster than
data rate, the serialization of table lookup and additions
is done with the optimized timing. The parameter
sample_ratio defines the ratio between the system clock
rate (sys_clk_frq) and the data sampling rate (data_rate),
as shown in EQ 8:
sample_ratio = sys_clk_frq/data_rate
EQ 8
CoreFIR supports folding when sample_ratio is greater
than or equal to nbits_in. The serialized operations of
table lookup and addition are done in nbits_in clock
cycles of the system clock, and the design is idle during
the rest of sample_ratio and nbits_in cycles. The
generator only requires that the sample_ratio be an
integer; the system clock rate is an exact multiple of the
data rate. Future releases may support a sample_ratio
less than nbits_in.
v3.0
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