COREFIR-XX Datasheet, PDF (11/14 Pages) Actel Corporation – CoreFIR Finite Impulse Response (FIR) Filter Generator

Clock and Reset
Input and Output Timing
CoreFIR
Clock
The CoreFIR generates a FIR filter design that uses only
positive-edge-triggered registers. The entire design is
fully synchronized using the positive edge of the input
clock clk, including the embedded RAM blocks (when
available).
Reset
The CoreFIR generates a design that uses only one active
low asynchronous reset. The entire design is
asynchronously reset by the input rstn.
I/O Timing Diagram of Normal FIR
Operation
The I/O timing under normal FIR operation is illustrated
in Figure 6. The labels s0 and s2 refer to the data
sampling point for input data, while s1 is the sampling
point for output data. Due to variations of the
configuration, you should refer to comments in the
generated module for t0 and t1. These parameters are
given in the number of the clock cycles of the input
clock, clk.
clk
datai_en
datai
datao_valid
datao
s0
t1
s1
s2
t0
0
1
0
Figure 6 • I/O Timing Diagram of Normal FIR Operation
I/O Timing Diagram of LUT Initialization
The I/O timing for LUT initialization is illustrated in
Figure 7. In this figure, s0 and s1 are the starting and
ending points for feeding coefficients, while s2 is the
sampling point for output ready. Due to the variation of
the configuration, refer to the comments inside the
generated module for t2, which are given in the number
of the clock cycles of the input clock clk.
s0
t2
s2
s1
clk
coefi_en
datai
0
1
2
ntaps-1
ready
Figure 7 • I/O Timing Diagram for LUT Initialization
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