COREFIR-XX Datasheet, PDF (6/14 Pages) Actel Corporation – CoreFIR Finite Impulse Response (FIR) Filter Generator

CoreFIR
Input Buffers
The Input Buffers block stores the input data which
contains ntaps data points, where ntaps is the number of
taps of the FIR filter. The Input Buffers block also
circulates the data bits to address the DA Lookup Tables
(LUTs) required by the DA algorithm. An optional
function of the input buffers block is to share its storage
with the DA LUT generator. The coefficients used in
computing the LUT content can be stored in the input
buffers when a design uses the embedded RAM blocks
for the LUTs.
DA Lookup Tables (LUTs)
The DA LUTs store the LUT contents for the distributed
algorithm. The generator implements the DA LUTs in two
ways: (1) synthesized ROM using FPGA cells; and (2)
embedded RAM blocks supported by the on-chip DA LUT
Generator. The first method is for an FPGA without
embedded RAM blocks, intended primarily for a small
FIR filter. The latter is for an FPGA with embedded RAM
blocks. FIR filters with a large number of taps may
require multiple LUTs.
Shifter and Accumulator
The Shifter and Accumulator perform additions with LUT
outputs and the alignments of LUT outputs required by
the DA algorithm. Multiple accumulators and shifters
may be needed to implement a FIR filter with a large
number of taps.
DA LUT Generator
The DA LUT Generator computes the LUT contents
required by the distributed arithmetic algorithm. It reads
the coefficients from the Input Buffers block and writes
the LUT words into the embedded RAM blocks. These
blocks are available only for designs that use embedded
RAM blocks as LUTs. The DA LUT Generator produces LUT
contents for multiple LUTs when implementing a FIR
filter with variable coefficients. Refer to "DA LUT
Generation" on page 10 and "I/O Timing Diagram of LUT
Initialization" on page 11 for detailed information on
initialization of the DA LUT.
Control
The state machine inside the Control block controls the
operations of all other blocks. It controls the input
buffers to ensure they operate based on the specified
system clock rate and sample rate, monitors input enable
and coefficient input enable, and circulates input data
bits to address the DA LUTs. It also controls the shifters
and accumulators to ensure they operate based on the
requested FIR configuration and DA algorithm. The
Control block coordinates the initialization of the LUTs
by the DA LUT generator when using embedded RAMs.
The Control logic is designed to support folding or
serialization of computation when the system clock rate
is substantially higher than the data sampling rate.
I/O Signal Description
The FIR filter generated by the CoreFIR Generator consists of the I/O signals defined in Table 3 (see Figure 3 on page 7).
Table 3 • I/O Signal Description
I/O Signal
Direction
Width
Polarity
Description
clk
Input
1
N/A
Master clock, positive edge
rstn
Input
1
Active low
Master reset, asynchronous
datai_en
datai¹
Input
Input
1
nbits_in¹
Active high
N/A
Input data enable
Input data or coefficients¹
datao_valid
datao
coefi_en²
ready²
Output
Output
Input
Output
1
nbits_out³
1
1
Active high
N/A
Active high
Active high
Output data valid
Output data
Coefficient input enable
Ready to input datai
Notes:
1. Input datai is also the input for coefficients for design using embedded RAMs as DA LUTs. In this case the width can be the
maximum of nbits_in and nbits_coef.
2. Ports coefi_en and ready are only available when coef_fixed = 0.
3. Refer to "Number of Bits of Output (nbits_out)" on page 8 for details.
4. Refer to Table 4 for nbits_in and nbits_coef.
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