COREFIR-XX Datasheet, PDF (1/14 Pages) Actel Corporation – CoreFIR Finite Impulse Response (FIR) Filter Generator

CoreFIR Finite Impulse Response (FIR)
Filter Generator
Product Summary
Intended Use
• Finite Impulse Response (FIR) Filter for Actel FPGAs
Key Features
• Core Generator
– Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
– Self-Checking – Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
– Multiplier-Free Computation
– Low Cost
– Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
– Serialized Computation when System Clock
Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
– Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA
with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without
Embedded RAMs
• Multiple DA lookup Tables to Split Large Number
of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision
Supported Families
• Fusion
• ProASIC3/E
• ProASIC^{PLUS ®}
• Axcelerator^®
• RTAX-S
• SX-A
• RTSX-S
Core Deliverables
• Evaluation Version
– RTL Code of a Sample Filter and Compiled RTL
Simulation Model Fully Supported in the Actel
Libero^® Integrated Design Environment (IDE)
• RTL Version
– A Microsoft Windows^® Binary Executable of
the CoreFIR Generator
– VHDL FIR Module
– VHDL Test Harness
Synthesis and Simulation Support
• Synthesis: Synplicity^®, Synopsys^® (Design
Compiler^®/FPGA Compiler^TM/FPGA Express^TM),
Exemplar^TM
• Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
Contents
Device Utilization and Performance ......................... 2
FIR Filter Using Distributed Arithmetic Algorithm ... 3
General Description ................................................... 5
Functional Block Description ..................................... 5
I/O Signal Description ................................................ 6
CoreFIR Generator Parameters .................................. 7
FIR Filter with Large Number of Taps ....................... 8
Clock and Reset ........................................................ 11
Input and Output Timing ........................................ 11
Appendix I: Sample Configuration File ................... 12
Ordering Information .............................................. 13
List of Changes ......................................................... 13
Datasheet Categories ............................................... 13
December 2005
v3.0
1
© 2005 Actel Corporation