COREFIR-XX Datasheet, PDF (10/14 Pages) Actel Corporation – CoreFIR Finite Impulse Response (FIR) Filter Generator

CoreFIR
DA LUTs Using FPGA Cells
Some Actel FPGA families such as SX-A and RTSX-S do not
have an embedded RAM implementation. In this case,
the CoreFIR Generator requires that the lookup table be
hard-coded as ROM using FPGA cells. This configuration
does not need the DA LUT Generator shown in Figure 2
on page 5. The generator selects this configuration when
the configurable parameter coef_fixed is set to 1 or the
configuration parameter fpga_family is not one of ax,
apa, or pa3.
DA LUTs Using Embedded RAM Blocks
Many Actel FPGA families have embedded RAM blocks.
The FIR generator takes advantage of these embedded
RAM blocks, and the DA LUTs are implemented using
these embedded RAM blocks. This configuration requires
additional overhead in that the embedded RAM blocks
must be initialized by a DA LUT Generator as shown in
Figure 2 on page 5. The generator selects this
configuration when the configurable parameter
coef_fixed is set to 0 and the configuration parameter
fpga_family is set to ax, apa, or pa3.
DA LUT Generation
The DA LUT Generator computes the LUT contents of the
distributed arithmetic algorithm. It reads the coefficients
from the Input Buffers block and writes the LUT words
into the embedded RAM blocks. This block is only
available when using embedded RAM blocks as LUTs –
when the configuration parameter coef_fixed is set to 0.
After the reset is complete, the DA LUT Generator will
wait for the Input Buffers block to signal that the
coefficients are loaded into the input buffers. Then the
DA LUT generator will compute the LUT words and write
them into the embedded RAM blocks. The DA LUT
Generator produces LUT contents for multiple LUTs when
implementing a FIR filter with a large number of taps.
The generator has only one computation engine, and
initializes multiple LUTs sequentially. After the
initialization of the RAM blocks, the output ready will go
high to let the system know that the FIR filter is ready to
accept data.
Input Buffering Scheme
The Input Buffers block always performs the functions
defined in "Input Coefficients" on page 10, but only
performs functions defined in "Input Data" on page 10
when the embedded RAM blocks are used as the DA LUTs
(when coef_fixed is set to 1).
Input Data
The input dataflow is designed to use the scheme shown
in Figure 5 to reduce the size of registers. The horizontal
movement of the input ensures the bits of the inputs
feed into the lookup table, and that it happens at every
cycle. Vertical movement of input data only occurs as the
most significant bit (MSB) is fed into lookup table, when
it switches to the next FIR data point.
x[n][3]
x[n][2]
x[n][1]
x[n][0]
x[n-1][3] x[n-1][2] x[n-1][1] x[n-1][0]
x[n-2][3] x[n-2][2] x[n-2][1] x[n-2][0]
x[n-3][3] x[n-3][2] x[n-3][1] x[n-3][0]
Figure 5 • Example of Input Buffering Scheme
Input Coefficients
The CoreFIR generator shares the input buffers for
coefficients input when embedded RAM blocks are used
as the DA LUTs. The configuration parameter coef_fixed
is set to 0. In this configuration, the width of the input
datai is the maximum of nbits_in and nbits_coef. The
input datai reads in coefficients when input coefi_en is
high. After enough coefficients are fed into the buffer,
coefi_en is ignored and the coefficients stay inside the
input buffers until the DA LUT Generator finishes the
initialization of the embedded RAM blocks.
User Interface
The generator executable reads one command line
parameter, which is the name of the configuration file. It
generates RTL code for the module and testbench based
on the parameters in the configuration file. Refer to
Table 4 on page 7 and "Appendix I: Sample
Configuration File" on page 12 for details of the
configuration file.
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