ZADCS0882 Datasheet, PDF (17/20 Pages) Zentrum Mikroelektronik Dresden AG – 8-Bit, 300ksps, Serial Output ADC Family

Datasheet
ZADCS0882/0842/0822 Family
Figure 16: Unipolar Transfer Function
Output Code
11 … 111
11 … 110
11 … 101
ZS = V(IN-)
FS = VREF +V(IN-)
1LSB =
VREF
256
00 … 010
00 … 001
00 … 000
0123
(ZS)
Input Voltage (LSB)
FS
FS-3/2 LSB
Figure 17: Bipolar Transfer Function
Output Code
01 … 111
01 … 110
00 … 011
00 … 001
00 … 000
11 … 111
11 … 110
11 … 101
ZS = V(IN-)
+ FS = ½VREF +V(IN-)
- FS = -½VREF +V(IN-)
1LSB =
VREF
256
10 … 001
10 … 000
-FS
ZS
Input Voltage (LSB)
+FS
+FS-3/2 LSB
2.5 Power Dissipation
The ZADCS08x2 family offers three different ways to
save operating current between conversions. Two differ-
ent software controlled power down modes can be acti-
vated to automatically shut-down the device after comple-
tion of a conversion. They differ in the amount of circuitry
that is powered down.
Software Power Down
Full Power Down Mode shuts down the entire analog part
of the IC, reducing the static IDD of the device to less
than 0.5µA if no external clock is provided at SCLK.
Fast Power Down mode is only useful with ZADCS08x2V
devices if the internal voltage reference is used. During
Fast Power-Down the bandgap and the VREFADJ output
buffer are kept alive while all other internal analog cir-
cuitry is shut down. The benefit of Fast Power Down
mode is a shorter turn on time of the reference compared
to Full Power-Down Mode. This is basically due to the
fact that the low pass which is formed at the VREFADJ
output by the internal 20kΩ resistor and the external
buffer capacitor of 47nF is not discharged in Fast Power-
Down Mode.
The settling time of the low pass at VREFADJ is about
6 ms to reach 8 bit accuracy. The Fast Power Down
mode omits this settling and reduces the turn on time to
about 200µs.
To wake up the IC out of either software power down
mode, it is sufficient to send a Start Bit while nCS is
LOW. Since micro controllers can commonly transfer full
bytes per transaction only, a dummy conversion is usually
carried out to wake the device.
In all application cases where an external reference volt-
age is supplied (basic ZADCS08x2 and ZADCS08x2V
with VREFADJ tied to VDD) there is no turn on time to be
considered. The first conversion is already valid. Fast
Power-Down and Full Power-Down Mode do not show
any difference in this configuration.
Hardware Power Down
The third power down mode is called Hardware Power-
Down. It is initiated by pulling the nSHDN pin LOW. If this
condition is true, the device will immediately shut down all
circuitry just as in Full Power Down-Mode.
The IC wakes up if nSHDN is tied HIGH. There is no
internal pull-up that would allow nSHDN to float during
normal operation. This ensures the lowest possible power
consumption in power down mode.
General Power Considerations
Even without activating any power down mode, the de-
vices out of the ZADCS08x2 family reduce their power
consumption between conversions automatically. The
comparator, which contributes a considerable amount to
the overall current consumption of the device, is shut off
as soon as a conversion is ended. It gets turned on at the
start of the next acquisition period. This explains the
difference between the IDDstatic and IDDactive meas-
urements shown in chapter 1.6 Typical Operating Char-
acteristics.
The average current consumption of the device depends
very much on the sampling frequency and the type of
protocol used to communicate with the device.
In order to achieve the lowest power consumption at low
sampling frequencies, it is suggested to keep the conver-
sion clock frequency at the maximum level of 3.3MHz and
to power down the device between consecutive conver-
sions. Figure 18 shows the characteristic current con-
sumption of the ZADCS08x2 family with external refer-
ence supply versus Sampling Rate
3 Layout
To achieve optimum conversion performance care must
be taken in design and layout of the application board. It
is highly recommended to use printed circuit boards in-
stead of wire wrap designs and to establish a single point
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
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