ZADCS0882 Datasheet, PDF (16/20 Pages) Zentrum Mikroelektronik Dresden AG – 8-Bit, 300ksps, Serial Output ADC Family

Datasheet
ZADCS0882/0842/0822 Family
Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V; qOP = qOPmin … qOPmax)
Parameter
Symbol Conditions
Min
SCLK Periode
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
nCS Fall to SCLK Setup
SCLK Fall to
DOUT & SSTRB Hold
SCLK Fall to
DOUT & SSTRB Valid
nCS Rise to
DOUT & SSTRB Disable
nCS Fall to
DOUT & SSTRB Enable
nCS Pulse Width High
tSCLK
tSCLKhigh
tSCLKlow
tDinSetup
tDinHold
tnCSSetup
tOutHold
CLoad = 20pF
tOutValid
CLoad = 20pF
tOutDisable CLoad = 20pF
tOutEnable CLoad = 20pF
tnCSHigh
303.0
151.5
151.5
30
10
30
10
10
100
Figure 15: Detailed Timing Diagram
Typ
Max Unit
ns
ns
ns
ns
ns
ns
ns
40 ns
60 ns
60 ns
ns
nCS
SCLK
DIN
SSTRB
DOUT
tnCSSetup
tSCLKhigh
tSCLK
tDINsetup
tOutEnable
tOutEnable
tSCLKlow
tDINhold
tnCSHigh
tOutValid
tOutHold
tOutDisable
ple/hold may drop to noticeable affect the conversion
result.
Further detailed timing information on the digital interface
is provided in Table 8 and Figure 15.
Output Code Format
ZADCS08x2 family devices do all support unipolar and
bipolar operation modes. The digital output code is
straight binary in unipolar mode. It ranges from 0x00 for
an input voltage difference of 0V to 0xFF for an input
voltage difference of VREF (Full Scale = FS). The first
code transition (0x00 à 0x01) occurs at a voltage equiva-
lent to ½ LSB, the last (0xFE à 0xFF) at VREF - 1.5 LSB.
See also Figure 16 for details.
In bipolar mode a two’s complement coding is applied.
Code transitions occur again halfway between successive
integer LSB values. The transfer function is shown in
Figure 17.
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
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