ZADCS0882 Datasheet, PDF (14/20 Pages) Zentrum Mikroelektronik Dresden AG – 8-Bit, 300ksps, Serial Output ADC Family

Datasheet
ZADCS0882/0842/0822 Family
Figure 11: 24-Clock External Clock Mode Timing (SPI™, QSPI™ and MICROWIRE™ compatible, fSCLK ≤ 3.3MHz)
nCS
SCLK
DIN
SSTRB
DOUT
tACQ
1
8
1
S A2 A1
(Start)
Idle
A0
UNI/
BIP
SGL/
DIF
PD1
PD0
Acquire
8
1
Conversion
B7 B6 B5 B4 B3 B2 B1 B0
(MSB)
(LSB)
8
Idle
Zero filled
Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission
nCS
SCLK
DIN
SSTRB
DOUT
1
8
1
S
A2
A1
A0
UNI/
BIP
SGL/
DIF
PD1
PD0
(Start)
Idle
Acquire
Conversion
8
1
8
S
A2
A1
A0
UNI/
BIP
SGL/
DIF
PD1
PD0
Result Output
Acquire
tCONV
B7 B6 B5 B4 B3 B2 B1 B0
(MSB)
(LSB)
Zero filled
Table 7: Control Byte Format
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Name
START
A2
A1
A0
UNI/BIP
SGL/DIF
PD1
PD0
Description
The Start Bit is defined by the first logic ‘1’ after nCS goes low.
Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multi-
plexer. For further details on the decoding see also Table 5 and Table 6.
Output Code Select Bit. The value of the bit determines conversion mode and output code
format.
‘1’ = unipolar - straight binary coding
‘0’ = bipolar - two’s complement coding
Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit
controls the setting of the input multiplexer
‘1’ = single ended - all channels CH0 … CH7 measured referenced to COM
‘0’ = differential - the voltage between two channels is measured
Power Down and Clock Mode Select Bits
PD1
PD0
Mode
0
0
Full Power-Down
0
1
Fast Power-Down
1
0
Internal clock mode
1
1
External clock mode
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
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