ZADCS0882 Datasheet, PDF (12/20 Pages) Zentrum Mikroelektronik Dresden AG – 8-Bit, 300ksps, Serial Output ADC Family

Datasheet
ZADCS0882/0842/0822 Family
Figure 7: Block diagram of input multiplexer
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Shown configuration
A2 … A0 = 0x000
IN+
Converter
IN-
Figure 8: Input voltage range in unipolar mode
VIN+
1.5*VREF
0xFF
VREF
0.5*VREF
Code Range
0x00
0V
VDD-VREF VIN-
Figure 9: Input voltage range for fully differen-
tial signals in bipolar mode
VCM
VREF
¾ VREF
VCM Range
COM
See Table 5 & Table 6
for Coding Schemes
SGL/DIF = HIGH
¼ VREF
0V
-VREF/2
0V
+VREF/2 VDIFF
In unipolar mode the voltage at IN+ must exceed the
voltage at IN– to obtain codes unequal to 0x00. The entire
8 bit transfer characteristic is then covered by IN+ if IN+
ranges from IN– to (IN– +Vref). Any voltage on IN+ > (IN–
+ Vref) results in code 0xFF. Code 0xFF is not reached,
if (IN– +Vref) > VDD + 0.2V because the input voltage is
clamped at VDD + 0.2V by ESD protection devices.
The voltage at IN– can range from -0.2V … ½ VREF with-
out limiting the Code Range, assuming the fore men-
tioned VDD condition is true. See also Figure 8 for input
voltage ranges in unipolar conversion mode.
In bipolar mode, IN+ can range from (IN– - Vref/2) to (IN–
+ Vref/2) keeping the converter out of code saturation.
For instance, if IN– is set to a constant DC voltage of
Vref/2, then IN+ can vary from 0V to VREF to cover the
entire code range. Lower or higher voltages of IN+ keep
the output code at the minimum or maximum code value.
Figure 9 shows the input voltage ranges in bipolar mode
when IN– is set to a constant DC voltage.
As explained before, converters out of the ZADCS08x2
family can also be used to convert fully differential input
signals that change around a common mode input volt-
age.
The bipolar mode is best used for such purposes since it
allows the input signals to be positive or negative in rela-
tion to each other.
The common mode level of a differential input signal is
calculated VCM = (V(IN+)+ V(IN–)) / 2. To avoid code clip-
ping or over steering of the converter, the common mode
level can change from ¼ VREF … ¾ VREF. Within this
range the peak to peak amplitude of the differential input
signal can be ± VREF/2.
The average input current on the analog inputs depends
on the conversion rate. The signal source must be capa-
ble of charging the internal sampling capacitors (typically
16pF on each input of the converter: IN+ and IN–) within
the acquisition time tACQ to the required accuracy. The
equivalent input circuit in sampling mode is shown in
Figure 6.
The following equation provides a rough hand calculation
for a source impedance RS that is required to settle out a
DC input signal referenced to AGND with 8 bit accuracy
in a given acquisition time
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
CHOLD+
IN+ _CIN
4pF _16pF
AGND
CHOLD-
RSW
3kΩ
RSW
VDC
Channel
Multiplexer
IN- _{CIN 4pF 16pF}
3kΩ
AGND
Figure 6: Equivalent input circuit during sampling
Copyright © 2008, ZMD AG, Rev. 1.1
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Information furnished in this publication is preliminary and subject to changes without notice.
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