ZADCS0882 Datasheet, PDF (11/20 Pages) Zentrum Mikroelektronik Dresden AG – 8-Bit, 300ksps, Serial Output ADC Family

Datasheet
ZADCS0882/0842/0822 Family
2 DETAILED DESCRIPTION
2.1 General Operation
The ZADCS08x2 family is a set of classic successive
approximation register (SAR) type converters. The archi-
tecture is based on a capacitive charge redistribution
DAC merged with a resistor string DAC building a hybrid
converter with excellent monotonicity and DNL properties.
The Sample & Hold function is inherent to the capacitive
DAC. This avoids additional active components in the
signal path that could distort the input signal or introduce
errors.
All devices in the ZADCS08x2 family build on the same
converter core and differ only in the number of input
channels and the availability of an internal reference
voltage generator. The ZADCS08x2V versions are
equipped with a highly accurate internal 1.25V bandgap
reference which is available at the VREFADJ pin. The
bandgap voltage is further amplified by an internal buffer
amplifier to 2.50V that is available at pin VREF. All other
versions come without the internal reference and the
internal buffer amplifier. They require an external refer-
ence supplied at VREF, with the benefit of considerably
lower power consumption.
A basic application schematic for ZADC0882V is shown
in Figure 4, for ZADCS0882 in Figure 5. ZADCS0882V
can also be operated with an external reference, if
VREFADJ is tied to VDD.
Table 5: Channel selection in Single Ended Mode
(SGL/DIF = HIGH)
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0 0 0 IN+
IN-
100
IN+
IN-
001
IN+
IN-
101
IN+
IN-
010
IN+
IN-
110
IN+
IN-
011
IN+
IN-
111
IN+ IN-
Figure 4: Basic application schematic for ZADCS0882V
2.2 Analog Input
The analog input to the converter is fully differential. Both
converter input signals IN+ and IN– (see Functional Block
diagram at front page) get sampled during the acquisition
period enabling the converter to be used in fully differen-
tial applications where both signals can vary over time.
The ZADCS08x2 family converters do not require that the
negative input signal be kept constant within ± 0.5LSB
during the entire conversion as is commonly required by
converters featuring pseudo differential operation only.
The input signals can be applied single ended, refer-
enced to the COM pin, or differential, using pairs of the
input channels. The desired configuration is selectable for
every conversion via the Control-Byte received on DIN
pin of the digital interface (see further description below)
A block diagram of the input multiplexer is shown in
Figure 7. Table 5 and Table 6 show the relationship of the
Control-Byte bits A2, A1, A0 and SGL/DIF to the configu-
ration of the analog multiplexer. The entire table applies
only to ZADCS0882 devices. For ZADCS0842 devices bit
A1 is don’t care, for ZADCS0822 devices A1 and A0 are
don’t care.
Both input signals IN+ and IN– are generally allowed to
swing between –0.2V and VDD+0.2V. However, depend-
ing on the selected conversion mode – uniploar or bipo-
lar – certain input voltage relations can limit the output
code range of the converter.
Table 6: Channel selection in Differential Mode
(SGL/DIF = LOW)
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0 0 0 IN+ IN-
001
IN+ IN-
010
IN+ IN-
011
IN+ IN-
1 0 0 IN- IN+
101
IN- IN+
110
IN- IN+
111
IN- IN+
Figure 5: Basic application schematic for ZADCS0882
µC
µC
ZADCS0882V
≥ 4.7µF
1 nCS
2 DIN
3 DGND
4 AGND
5 VREF
6 COM
7 CH0
8 CH1
9 CH4
10 CH5
SCLK 20
SSTRB 19
DOUT 18
nSHDN 17
VDD 16
VREFADJ 15
CH2 14
CH3 13
CH6 12
CH7 11
47nF
+2.7V to 5.25V
0.1µF 10µF
≥ 4.7µF
ZADCS0882
1 nCS
2 DIN
3 DGND
4 AGND
5 VREF
6 COM
7 CH0
8 CH1
9 CH4
10 CH5
SCLK 20
SSTRB 19
DOUT 18
nSHDN 17
VDD 16
n.c. 15
CH2 14
CH3 13
CH6 12
CH7 11
+2.7V to 5.25V
0.1µF 10µF
Single-ended or differential
analog inputs, 0V … +2.5V
Single-ended or differential
analog inputs, 0V … +VREF
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
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