Z16C30_08 Datasheet, PDF (51/102 Pages) Zilog, Inc. – CMOS USC Universal Serial Controller

Z16C30
Product Specification
47
In the USC, the IP bit signals that an interrupt request is being serviced. If an IUS is set, all
interrupt sources of lower priority within the channel and external to the channel are pre-
vented from requesting interrupts. The internal interrupt sources are inhibited by the state
of the internal daisy chain, while lower priority devices are inhibited by the IEO output of
the channel being pulled Low and propagated to subsequent peripherals. An IUS bit is set
during an interrupt acknowledge cycle if there are no higher priority devices requesting
interrupts.
There are six sources of interrupt in each channel: Receive Status, Receive Data, Transmit
Status, Transmit Data, I/O Status, and Device Status, prioritized in that order within the
channel. There are six sources of Receive Status interrupt, each individually enabled:
exited hunt, idle line, break/abort, code violation/end-of-transmission/end-of-frame, parity
error, and overrun error. The Receive Data interrupt is generated whenever the receive
FIFO fills with data beyond the level programmed in the Receive Interrupt Control Regis-
ter (RICR).
There are six sources of Transmit Status interrupt, each individually enabled: preamble
sent, idle line sent, abort sent, end-of-frame/end-of-transmission sent, CRC sent, and
underrun error. The Transmit Data interrupt is generated whenever the transmit FIFO
empties below the level programmed in the Transmit Interrupt Control Register (TICR).
The I/O Status interrupt serves to report transitions on any of six pins. Interrupts are gener-
ated on either or both edges with separate selection and enables for each pin. The pins pro-
grammed to generate I/O Status interrupts are RxC, TxC, RxREQ, TxREQ, DCD, and
CTS. These interrupts are independent of the programmed function of the pins. The
Device Status interrupt has four separately enabled sources: receive character count FIFO
overflow, DPLL sync acquired, BRG1 zero count, and BRGO zero count.
Block Transfer Mode
The USC accommodates block transfers through DMA through the RxREQ, TxREQ,
RxACK, and TxACK pins. The RxREQ signal is activated when the fill level of the
receive FIFO exceeds the value programmed in the RICR. The DMA may respond with
either a normal bus transaction or by activating the RxACK pin to read the data directly
(fly-by transfer). The TxREQ signal is activated when the empty level of the transmit
FIFO falls below the value programmed in the TICR. The DMA may respond either with a
normal bus transaction or by activating the TxACK pin to write the data directly (fly-by
transfer). The RxACK and TxACK pin functions for this mode are controlled by the Hard-
ware Configuration Register (HCR). Then using the RxACK and TxACK pins to transfer
data, no chip select is necessary; these are dedicated strobes for the appropriate FIFO.
Programming
The registers in each USC channel are programmed by the system to configure the chan-
nels. Before this can occur, however, the system must program the bus interface by writing
to the Bus Configuration Register (BCR). The BCR has no specific address and is only
DS007902-0708
PRELIMINARY
Functional Description