Z16C30_08 Datasheet, PDF (5/102 Pages) Zilog, Inc. – CMOS USC Universal Serial Controller

Z16C30
Product Specification
1
Architectural Overview
Features
The key features of Zilog’s Z16C30 device include:
• Two Independent 0-to-10 Mbps Full-Duplex Channels, each with Two Baud Rate Gener-
ators and One digital phase-locked loop (DPLL) for Clock Recovery
• 32-byte Data FIFO’s for each Receiver and Transmitter
• 110 ns Bus Cycle Time, 16-bit Data Bus Bandwidth
• Multi-Protocol Operation under Program Control with Independent Mode Selection for
Receiver and Transmitter
• Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop Bits/Character in 1/16-bit Incre-
ments, Programmable Clock Factor, Break Detect and Generation, Odd, Even, Mark,
Space or no Parity and Framing Error Detection, Supports One Address/Data Bit and MIL
STD 1553B Protocols
• Byte Oriented Synchronous Mode with One to Eight Bits/Character, Programmable Idle
Line Condition, Optional Receive Sync Stripping; Optional Preamble Transmission, 16-
or 32-bit CRC, and Transmit-to-Receive Slaving (for X.21)
• Bisync Mode with 2- to 16-bit Programmable Sync Character, Programmable Idle Line
Condition, Optional Receive Sync Stripping, Optional Preamble Transmission, 16- or 32-
bit CRC
• Transparent Bisync Mode with EBCDIC or ASCII Character Code, Automatic CRC Han-
dling, Programmable Idle Line Condition, Optional Preamble Transmission, Automatic
Recognition of DLE, SYN, SOH, ITX, ETX, ETB, EOT, ENQ, and ITB
• External Character Sync Mode for Receive
• HDLC/SDLC Mode with Eight-Bit Address Compare, Extended Address Field Option,
16- or 32-bit CRC, Programmable Idle Line Condition, Optional Preamble Transmission
and Loop Mode
• DMA Interface with Separate Request and Acknowledge for Each Receiver and Transmit-
ter
• Channel Load Command for DMA Controlled Initialization
• Flexible Bus Interface for Direct Connection to Most Microprocessors, User Programma-
ble for 8 or 16 Bits Wide, Directly Supports 680X0 Family or 8X86 Family Bus Interfaces
• Low Power CMOS
• 68-Pin PLCC/100-Pin VQFP Packages
DS007902-0708
PRELIMINARY
Architectural Overview