Z16C30_08 Datasheet, PDF (50/102 Pages) Zilog, Inc. – CMOS USC Universal Serial Controller

Z16C30
Product Specification
46
Clock Multiplexer
The clock multiplexer in each channel selects the clock source for the various blocks in the
channel and selects an internal clock signal to potentially be sent to either the RxC or TxC
pin.
Test Modes
The USC can be programmed for local loopback or auto echo operation. In local loopback,
the output of the transmitter is internally routed to the input of the receiver. This allows
testing of the USC data paths without any external logic. Auto echo connects the RxD pin
directly to the TxD pin. This is useful for testing serial links external to the USC.
I/O Interface Capabilities
The USC offers the choice of polling, interrupt (vectored or nonvectored) and block trans-
fer modes to transfer data, status and control information to and from the CPU.
Polling
All interrupts are disabled. The registers in the USC are automatically updated to reflect
current status. The CPU polls the Daisy Chain Control Register (DCCR) to determine sta-
tus changes and then reads the appropriate status register to find and respond to the change
in status. USC status bits are grouped according to function to simplify this software
action.
Interrupt
When a USC responds to an interrupt acknowledge from the CPU, an interrupt vector may
be placed on the data bus. This vector is held in the Interrupt Vector Register (IVR). To
speed interrupt response time, the USC modifies three bits in this vector to indicate which
type of interrupt is being requested.
Each of the six sources of interrupts in each channel of the USC (Receive Status, Receive
Data, Transmit Status, Transmit Data, I/O Status, and Device Status) has three bits associ-
ated with the interrupt source: Interrupt Pending (IP), Interrupt-Under-Service (IUS), and
Interrupt Enable (IE). If the IE bit for a given source is set, that source can request inter-
rupts. Note that individual sources within the six groups also have interrupt enable bits
which are set for the particular source. In addition, there is a Master Interrupt Enable
(MIE) bit in each channel which globally enables or disables interrupts within the channel.
The other two bits are related to the interrupt priority chain. A channel in the USC may
request an interrupt only when no higher priority interrupt source is requesting one, e.g.,
when IEI is High for the channel. In this case the channel activates the INT signal. The
CPU then responds with an interrupt acknowledge cycle, and the interrupting channel
places a vector on the data bus.
DS007902-0708
PRELIMINARY
Functional Description