Z16C30_08 Datasheet, PDF (49/102 Pages) Zilog, Inc. – CMOS USC Universal Serial Controller

Z16C30
Product Specification
45
ically loaded into a four-deep FIFO. This allows DMA transfer of data to proceed without
CPU intervention at the end of a received message, as the values in the FIFO allow the
CPU to determine message boundaries in memory. Similarly, the transmit character
counter is loaded either under software control or automatically at the beginning of a
transmit message. The counter is decremented with each write to the transmit FIFO. When
the counter has decremented to 0, and that byte is sent, the transmitter automatically termi-
nates the message in the appropriate fashion (usually CRC and the closing flag or sync
character) without requiring CPU intervention.
Baud Rate Generators
Each channel in the USC contains two baud rate generators. Each generator consists of a
16-bit time constant register and a 16-bit down counter. In operation, the counter decre-
ments with each baud rate generator clock, with the time constant automatically reloaded
when the count reaches zero. The output of the baud rate generator toggles when the
counter reaches a count of one-half of the time constant and again when the counter
reaches zero.A new time constant may be written at any time but the new value will not
take effect until the next load of the counter. The outputs of both baud rate generators are
sent to the clock multiplexer for use internally or externally. The baud rate generator out-
put frequency is related to the baud rate generator input clock frequency by the following
equation:
Output frequency = Input frequency/(time constant + 1)
This allows an output frequency in the range of 1 to 1/65536 of the input frequency, inclu-
sive.
Digital Phase-Locked Loop
Each channel in the USC contains a Digital Phase-Locked Loop (DPLL) to recover clock
information from a data stream with NRZI or Biphase encoding. The DPLL is driven by a
clock that is nominally 8, 16 or 32 times the receive data rate. The DPLL uses this clock,
along the data stream, to construct a clock for the data. This clock may then be routed to
the receiver, transmitter, or both, or to a pin for use externally. In all modes, the DPLL
counts the input clock to create nominal bit times. As the clock is counted, the DPLL
watches the incoming data stream for transitions. Whenever a transition is detected, the
DPLL makes a count adjustment (during the next counting cycle), to produce an output
clock which tracks the incoming bit cells. The DPLL provides properly phased transmit
and receive clocks to the clock multiplexer.
Counters
Each channel contains two 5-bit counters, which are programmed to divide an input clock
by 4, 8, 16, or 32. The inputs of these two counters are sent to the clock multiplexer. The
counters are used as prescalers for the baud rate generators, or to provide a stable transmit
clock from a common source when the DPLL is providing the receive clock.
DS007902-0708
PRELIMINARY
Functional Description