Z16C30_08 Datasheet, PDF (43/102 Pages) Zilog, Inc. – CMOS USC Universal Serial Controller

Z16C30
Product Specification
39
Table 7. Z16C30 System Timing
No Symbol
Parameter
Min
1 TdRxC(REQ) RxC Rise to RxREQ Valid Delay
2 TdRxC(RxC) TxC Rise to RxC as Receiver Output Valid Delay
3 TdRxC(INT) RxC Rise to INT Valid Delay
4 TdTxC(REQ) TxC Fall to TxREQ Valid Delay
5 TdTxC(TxC) RxC Fall to TxC as Transmitter Output Valid
Delay
6 TdTxC(INT) TxC Fall to INT Valid Delay
7 TdEXT(INT) CTS, DCD, TxREQ, RxREQ transition to INT
Valid Delay
Notes
1. RxC is RxC or TxC, whichever is supplying the receive clock.
2. TxC is TxC or RxC, whichever is supplying the transmit clock.
Max Units Notes
100 ns
1
100 ns
1
100 ns
1
100 ns
2
100 ns
2
100 ns
2
100 ns
Architecture
The USC internal structure includes two completely independent full-duplex serial chan-
nels, each with two baud rate generators, a digital phase-locked loop for clock recovery,
transmit and receive character counters and a full-duplex DMA interface. The two serial
channels share a common bus interface. The bus interface is designed to provide easy
interface to most microprocessors, whether they employ a multiplexed or nonmultiplexed,
8-bit or16-bit bus structure. Each channel is controlled by a set of thirty 16-bit registers,
nearly all of which are readable and writable. There is one additional 16-bit register in the
bus interface used to configure the nature of the bus interface. The BCR functions are
shown as follows:
DS007902-0708
PRELIMINARY
Electrical Characteristics