Z86230 Datasheet, PDF (48/61 Pages) Zilog, Inc. – ADVANCED VIOLENCE BLOCKING AND NTSC 21 XDS

ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
TABLE 38. NON-STANDARD VIDEO SIGNALS
Parameter
Conditions
H Timing
Vertical Sync
Signal
Phase Step (Head Switch) ±10 µs maximum
Fh Deviation (long term) ±0.5% maximum
Fh p-p Deviation (short term) ±0.3% maximum
The internal sync circuits lock to all 525- or 625-line
signals that exhibit a vertical sync pulse that meets the
following conditions:
1. It is at least 3H ±0.5H wide.
2. It starts at the proper 2H boundary for its field.
3. If equalizing pulse serrations are present, they
must be less than 0.125H in width.
Minimum Signal-
to-Noise
The Z86230 functions down to a 25 dB signal-to-noise
ratio (CCIR-weighted) with one error per row or better
at that level.
Ratio to Composite Input
Video
8.5.2 HIN/XIN Signal Input
Table 39. HIN/XIN Signal Input
Mode
1. HIN
Input
(Video Lock Mode)
(HIN Lock Mode)
Parameter
Amplitude
Polarity
Frequency
Amplitude
Polarity
Frequency
2. XIN
Input
(XTAL)
(Clock)
Frequency
Frequency
tolerance
Amplitude
Frequency
Conditions
CMOS level signal where Low ≤ 0.2 V_CC
Any
15,734.263 Hz @ 3%
CMOS level signal where Low ≤ 0.2 V_CC
Any
Same as Display Horizontal Flyback (HFB)
pulse
32.768 KHz
±20ppm @ T_A = 25C, CL = 12.5pF
CMOS level signal where Low ≤ 0.2 V_CC
32.768 kHz ±2%
48
Z86230—PRELIMINARY
PS000400-TVC0499