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Z86230 Datasheet, PDF (18/61 Pages) Zilog, Inc. – ADVANCED VIOLENCE BLOCKING AND NTSC 21 XDS
SERIAL COMMUNICATIONS INTERFACE
I2C BUS OPERATION
4. SERIAL COMMUNICATIONS INTERFACE
Commands and data are sent to and from the Z86230 through its I2C serial com-
munications interface. This port is the path for setting the configuration and oper-
ational modes of the device. The interface is also used as the port for outputting
the recovered XDS data.
4.1 I2C BUS OPERATION
The Z86230 supports a bidirectional 2-wire bus and data transmission protocol.
The bus is controlled by the master device, which generates the serial clock
(SCLK), controls the bus access, and generates the START and STOP conditions.
The serial data (SDA) pin is the bidirectional data line. The Z86230 is a slave
device with two possible slave addresses. When the I2C SEL pin is Low, the slave
address is 28h for WRITE and 29h for READ. When the I2C SEL pin is High,
the slave address is 2Ah for WRITE and 2Bh for READ.
The Z86230 can receive or transmit data under control of the master device. Com-
munication is initiated when the master device sends the START condition fol-
lowed by the Z86230 Slave Address READ byte or Slave Address WRITE byte.
The Z86230 responds with an Acknowledge.
The I2C RD/WR bit is the Least Significant Bit (LSB) of the I2C addresses listed
below in Table 4.
TABLE 4. Z86230 I2C SLAVE ADDRESSES
READ
WRITE
1st I2C Address
29h
28h
2nd I2C Address
2Bh
2Ah
NOTE: Low(0) on pin 1 selects the 1st I2C Address; HIGH(1) on pin 1 selects the
2nd I2C Address.
4.1.1 The I2C Bus Protocol
The Bus Protocol requires that:
1. Data transfer can only be started when the bus is not busy.
2. During data transfer, data transitions must not occur while the clock is High.
4.1.2 Bus Conditions
Bus Conditions are defined as:
Not Busy. Data and Clock lines are both High.
START. A High-to-Low transition of the SDA line while the SCLK line is High.
STOP. A Low-to-High transition of the SDA line while the SCLK line is High.
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Z86230—PRELIMINARY
PS000400-TVC0499