Z86230 Datasheet, PDF (22/61 Pages) Zilog, Inc. – ADVANCED VIOLENCE BLOCKING AND NTSC 21 XDS

SERIAL COMMUNICATIONS INTERFACE
I²C BUS OPERATION
4.1.7 STOP Condition
A Low-to-High transition of SDA with SCLK High is a STOP condition which ter-
minates all communications.
4.1.8 Acknowledge
All address and data words are serially transmitted to and from the Z86230 in
eight bit words. A ninth bit time is used for the Acknowledge. The acknowledging
device pulls the SDA bus Low during the ninth bit. A Not Acknowledge (NACK)
is returned by SDA = High during the ninth clock time.
FIGURE 6. I²C SERIAL TIMING
t_F
SCLK
t_SU.STA
t_High t_Low
t_R
t_SU.DAT
t_HD.STA
SDA (IN)
t_AA
t_HD.DAT
t_DH
SDA (OUT)
t_SU.STO
t_BUF
TABLE 6. I²C SERIAL TIMING MIN/MAX
Symbol
f_SCLK
t_LOW
t_High
t_R
t_F
t_AA
t_BUF
t_HD.STA
t_SU.STA
t_HD.DAT
t_SU.DAT
t_SU.STO
t_DH
t_I
Parameter
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
SDA and SCL Rise Time
SDA and SCL Fall Time
Clock Low to Data Out Valid
Bus Free Time
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Input Filter Time Constant
Min
Max Units
100
kHz
4.7
–
ms
4.0
–
ms
–
1.0
ms
–
300
ns
0.1
3.5
ms
4.7
–
ms
4.0
–
ms
4.7
–
ms
0
–
ms
250
–
ns
4.7
–
ms
100
–
ns
100
ns
22
Z86230—PRELIMINARY
PS000400-TVC0499