Z86230 Datasheet, PDF (12/61 Pages) Zilog, Inc. – ADVANCED VIOLENCE BLOCKING AND NTSC 21 XDS

ARCHITECTURAL OVERVIEW
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
1.1.6 Decoder Control Circuit
The Decoder Control circuit block is the users communications port. This circuit
converts the information from the control port into the internal control signals
required to establish the operating mode of the decoder.
The Z86230 responds to its slave address for both the READ and WRITE condi-
tions. If the READ bit is Low (indicating a WRITE sequence), then the Z86230
responds with an Acknowledge. The master should then send an address byte fol-
lowed by a data byte. If the READ bit is High (indicating a READ sequence), then
the Z86230 responds with an Acknowledge followed sequentially by a status byte
and a data byte. READ data is only available through indirect addressing. WRITE
addressing exhibits both indirect and direct modes. The busy bit in the status byte
indicates if the WRITE operation is completed or if READ data is available.
1.1.7 Voltage/Current Reference
The Voltage/Current reference circuit uses an externally connected resistor to
establish the reference levels that are used throughout the Z86230. For a minimal
investment, the use of an external resistor can also provide improved internal pre-
cision.
FIGURE 2. VOLTAGE/CIRCUIT REFERENCE
Pin 10
RREF
10 kΩ ±2%
GND
12
Z86230—PRELIMINARY
PS000400-TVC0499