Z86230 Datasheet, PDF (25/61 Pages) Zilog, Inc. – ADVANCED VIOLENCE BLOCKING AND NTSC 21 XDS

REGISTERS SUMMARY
CONTROL REGISTERS
6. CONTROL REGISTERS
Information controlling the setup and operation of the Z86230 are maintained in
several registers. The user may read or alter the contents of these registers as
required.
All register diagrams indicated in this section incorporate the following conven-
tions, unless otherwise noted:
• R = Read, W = Write, X = Indeterminate, and res = Reserved
• All register bits marked as res must be set to Low(0)
6.1 REGISTERS SUMMARY
6.1.1 Serial Status Register
TABLE 11. SERIAL STATUS REGISTER (ADDRESS NOT REQUIRED)
Bit
7
6
5
4
3
2
1
0
RDY DAV res WOVR INTR ROVR FLD LOCK
R/W
R
RR
R
R
R
R
R
D₀–LOCK. Active High, indicating that the internal sync circuits are locked. May
be used as an indication of the presence of a video signal.
D₁–FLD. Signals the current video field. Low = Field 2, High = Field 1.
D₂–ROVR. Active High, indicating that the data available in the output buffer is
not read out and new data is written over it.
D₃–INTR. Active High, indicating that an interrupt other than DAV is pending.
Reserved.
D₄–WOVR. Active High, indicating a serial input data overrun.
D₅-Res. Reserved.
D₆-DAV. Active High, indicating that data is available to be read out.
D₇–RDY. Active High, indicating that the port input buffer is empty. Only the
NOP, RESET and READ instructions may be sent if RDY is Low.
6.1.2 Configuration Register
TABLE 12. CONFIGURATION REGISTER (ADDRESS = 00h)
Bit
7
6
5
4
3
2
1
0
res res res res res res res TVS
R/W
R
RR
R
R R/W R R/W
PS000400-TVC0499
Z86230—PRELIMINARY
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