Z86230 Datasheet, PDF (19/61 Pages) Zilog, Inc. – ADVANCED VIOLENCE BLOCKING AND NTSC 21 XDS

I²C BUS OPERATION
SERIAL COMMUNICATIONS INTERFACE
Acknowledge. When addressed, the receiving device must output an Acknowl-
edge after the reception of each byte. The master device must generate the clock
for the Acknowledge bit. Acknowledge is SDA = Low. Not Acknowledge (NACK)
is SDA = High.
Data. The data (SDA) is output by the transmitting device on the falling edge of
SCLK, MSB first. The receiving device interprets the data, MSB first, on the rising
edge of SCLK.
Communication with the Z86230 is initiated when the master device sends the
Z86230 slave address following a START condition. The Z86230 has a preset,
single, seven-bit slave address. The Z86230 responds with an Acknowledge. The
eighth bit of the slave address is driven High for READ operations and Low for
WRITE operations.
4.1.3 Writing to the I²C Bus
Commands and data are written to the Z86230 using the I²C bus interface. The
device is enabled when an I²C START condition, followed by its Slave Address
WRITE byte, is received. A WRITE operation is ended and the bus is disabled upon
the receipt of an I²C STOP condition. Any number of command bytes, up to 32,
may be sent after the device is WRITE-enabled. Each of these commands is either
1 or 2 bytes in length. The device executes the commands in order of receipt.
Overflowing the 32 byte buffer causes improper operation. The RDY bit of the
Serial Status Register (SSR) may be read to determine if there is room in the com-
mand buffer for at least 2 bytes of command data. The Status register data is out-
put immediately following the receipt of the Slave Address READ.
The first byte of a 2-byte command is always written first. The master’s sequence
for writing a 2-byte command, followed by a 1-byte command is displayed in the
following example:
Start
Slave_Address_Write/Slave ACK
CMD1_Write/Slave ACK
DATA1_Write/Slave ACK
CMD2_Write/Slave ACK
Stop
PS000400-TVC0499
Z86230—PRELIMINARY
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