Z8E520 Datasheet, PDF (33/43 Pages) Zilog, Inc. – 1.5 MBPS USB Device Controller

Zilog
Z8E520/C520
1.5 MBPS USB Device Controller
Watch-Dog Timer. The WDT can be programmed at any- trolled by the Interrupt Priority register. All interrupts are
time in the program operation.
vectored through locations in the program memory. When
Default value (Reset) = 98 ms
1 ^{an interrupt machine cycle is activated an interrupt request}
is granted. All of the subsequent interrupts are thus dis-
The RC oscillator is under firmware control. If the oscillator
is enabled during USB Suspend/Chip Stop Mode, the de-
vice will be periodically woke up by the WDT timeout. If the
application does not require “motion detect,” the current
that drives the internal oscillator/WDT can be saved.
abled, saving the Program Counter and status flags, and
branching to the program memory vector location reserved
for that interrupt. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request.
WDT Control Registers. Select time-out values for the
WDT are programmable –0 to +100%.
EMI. Lower EMI on the Z8E520 is achieved through circuit
modifications.
Interrupts. The Z8E520 has six different interrupts. These
interrupts are maskable and prioritized (Figure 19 ). The
The Z8E520 also accepts external clock from XTAL IN pin
(Figure 20).
six sources are divided as follows:
Priority
0
1
2
3
4
5
IRQ
TCO
TC1
TC2
COMM HIGH
COMM LOW
Port
XTAL1 (in)
XTAL2 (out)
.
Figure 20. Oscillator Configuration
IRQ0–IRQ4
6
Power-On-Reset (POR). A timer circuit is triggered by the
system oscillator and is used for the Power-On Reset
I RQ
(POR) timer function. The POR time allows V_CC and the os-
cillator circuit to stabilize before instruction execution be-
gins. POR period is defined as:
I MR
6
Global
Interrupt
Enable
Interrupt
Request
Vector Select
Figure 19. Interrupt Block Diagram
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
POR (ms) = 98 ms
The POR timer circuit is a one-shot timer triggered by pow-
er fail to Power OK status. The POR time is a nominal 100
ms at 6 MHz. The POR time is bypassed after Stop-Mode
Recovery.
HALT. HALT turns off the internal CPU clock, but not the
oscillator. The counter/timer and external interrupts
IRQ0–5 remain active. The Z8E520 recovers by interrupts,
either externally or internally.
USB Reset. Detection by the SIE of a reset from the Host
will cause the chip to reset. The reset will be remembered
so that the program can decide the source of the reset.
The USB Reset will act even if the chip is in the STOP
mode.
DS97KEY2005
PRELIMINARY
33