Z8E520 Datasheet, PDF (28/43 Pages) Zilog, Inc. – 1.5 MBPS USB Device Controller

Z8E520/C520
1.5 MBPS USB Device Controller
Zilog
COMMUNICATION REGISTER DEFINITIONS (NON-USB MODES)
The following definitions describe in detail the specific non-
USB mode registers as illustrated in Figure 16.
PORT A, PORT B: Same as USB mode. Port B6 and B7
are I/O in the GPIO Mode.
SIE MODE: Same as USB mode.
s RCV COMM ERROR: Indicates that a communications
error occurred while receiving a byte, resulting in a
framing or parity error. In PS/2 mode, it may also
indicate that the host aborted its own transmission.
s RCV DONE: Indicates that RCV PACKET SIZE bytes
have been received since RCV READY was set.
LOW PRIORITY INTR: This register contains the IRQ
flags of a low-priority communications interrupt.
Read/Write.
LOW PRIORITY MASK: This register contains mask bits
for the IRQ sources specified in the LOW PRIORITY INTR
register. A set bit indicates that the corresponding interrupt
source is unmasked.
s XMIT COMM ERROR: Indicates that a communications
error occurred while transmitting a byte. Valid only when
the SIE is in PS/2 mode. Indicates that the host aborted
the transfer.
s XMIT DONE: Indicates that XMIT PACKET SIZE bytes
have been sent since XMIT READY was set.
COMM CSR: Controls the SIE in PS/2 and RS232-C
mode.
s XMIT READY: Indicates to the SIE that the XMIT buffer
is valid. Cleared by SIE when XMIT DONE is set.
Cannot be cleared by firmware. Read/Write.
s RCV READY: Indicates to the SIE that the most recent
packet received has been handled. Cleared by the SIE
after RCV DONE is set. Cannot be cleared by firmware.
Read/Write.
s RCV PACKET SIZE: Number of bytes to receive before
BYTE RECEIVED interrupt. Value may not exceed the
size specified in RCV BUFFER SIZE. A “0” indicates that
the packet size = the buffer size. Read/Write.
HIGH PRIORITY INTR: This register contains the IRQ
source flags of a low-priority communications interrupt.
The ISR should check these bits to determine the cause of
the interrupt. Read/Write.
HIGH PRIORITY MASK: This register contains mask bits
for the IRQ sources specified in the HIGH PRIORITY INTR
register. A set bit indicates that the corresponding interrupt
source is unmasked.
s OVERRUN ERROR: Indicates that RCV READY was
clear when RCV DONE was set.
s XMIT PACKET SIZE: The number of bytes to send
before the XMIT DONE interrupt. A “0” indicates that the
packet size = the buffer size
s LAST BYTE RECEIVED OFFSET: Indicates the offset
in the RECEIVE buffer of the most recent byte received.
Read only.
s NEXT SEND BYTE OFFSET: Indicates the offset in the
XMIT buffer of the next byte to be sent. If the host has
aborted a PS/2 transmission, it is the offset of the byte
that was aborted. Read only.
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PRELIMINARY
DS97KEY2005