Z8E520 Datasheet, PDF (31/43 Pages) Zilog, Inc. – 1.5 MBPS USB Device Controller

Zilog
Z8E520/C520
1.5 MBPS USB Device Controller
PORT REGISTER DEFINITIONS
The following definitions describe in detail the specific port SINK: Indicates the level of current drawn by the current
registers as illustrated in Figure 17.
1 ^{sink on the pin. When SINK ≠ 0, the n-channel output tran-}
sistor is disabled. When SINK = 0, the sink is off and the n-
WAKE: When set, this pin is capable of waking the device _{channel output transistor may be enabled according to the}
on any edge.
OUTPUT bit.
PUSH/PULL: When set, this pin is a push-pull output.
When clear, this pin is an open-drain output. Ignored if
OUTPUT is clear.
PULLUP ON: When set, the pull-up resistor is on.
DIVIDER: Selects one of the three voltage dividers to be
placed on the pin. Divider 0 indicates no divider.
VREF: Indicates the voltage reference level for the com-
parator. Ignored if COMP ENABLED is clear.
OUTPUT: When set, the pin’s output drivers are enabled.
However, the pin may be read at any time regardless of the
configuration.
COMP ENABLE: When set, the comparator is powered.
When clear, the comparator and VREF circuitry are pow-
ered down.
FUNCTIONAL DESCRIPTIONS
Counter/Timers. For the Z8E20, 8-bit timers T0 and T1
are available to function as a pair of independent 8-bit
standard timers, or they can be cascaded to function as a
16-bit PWM timer. In addition, 8-bit timers T2 and T3 are
provided but they can only operate in cascade to function
as a 16-bit standard timer (Figure 18).
Each 8-bit timer is provided a pair of registers, which are
both readable and writable. One of the registers is defined
to contain the auto-initialization value for the timer, while
the second register contains the current value for the timer.
When a timer is enabled, the timer will decrement whatev-
er value is currently held in its count register, and will then
continue decrementing until it reaches 0, at which time an
interrupt will be generated and the contents of the auto-ini-
tialization register are optionally copied into the count val-
ue register. If auto-initialization is not enabled, the timer
will stop counting upon reaching 0 and control logic will
clear the appropriate control register bit to disable the tim-
er. This occurrence is referred to as “single-shot” opera-
tion. If auto-initialization is enabled, the timer will continue
counting from the initialization value. Software should not
attempt to use registers that are defined as having timer
functionality.
Software is allowed to write to any register at any time, but
it is not recommended that timer registers be updated
while the timer is enabled. If software updates the count
value while the timer is in operation, the timer will continue
counting based upon the software-updated value. This oc-
currence can produce strange behavior if the software up-
date occurred at exactly the point that the timer was reach-
ing 0 to trigger an interrupt and/or reload.
Similarly, if software updates the initialization value regis-
ter while the timer is active, the next time that the timer
reaches 0, it will be initialized using the updated value.
Again, strange behavior could result if the initialization val-
ue register is being written while the timer is in the process
of being initialized. Whether initialization is done with the
new or old value is a function of the exact timing of the
write operation. In all cases, the Z8E520 will prioritize the
software write above that of a decremented writeback.
However, when hardware clears a control register bit for a
timer that is configured for single-shot operation; the clear-
ing of the control bit will override a software write. Reading
either register can be done at any time, and will have no
effect on the functionality of the timer.
If a timer pair is defined to operate as a single 16-bit entity,
the entire 16-bit value must reach 0 before an interrupt is
generated. In this case, a single interrupt will be generat-
ed, and the interrupt will correspond to the even 8-bit time.
For example, timers T2 and T3 are cascaded to form a sin-
gle 16-bit timer, so the interrupt for the combined timer will
be defined to be that of timer T2 rather than T3. When a
timer pair is specified to act as a single 16-bit timer, the
even timer registers in the pair (timer T0 or T2) will be de-
fined to hold the timer’s least significant byte; while the odd
timer in the pair will hold the timer’s most significant byte.
In parallel with the posting of the interrupt request, the in-
terrupting timer’s count value will be initialized by copying
the contents of the auto-initialization value register to the
count value register.
Note: Any time that a timer pair is defined to act as a
single 16-bit timer, that the auto-reload function will be
performed automatically. All 16-bit timers will continue
counting while their interrupt requests are active, and will
operate in a free-running manner.
If interrupts are disabled for a long period of time, it is pos-
sible for the timer to decrement to 0 again before its initial
interrupt has been responded to. This occurrence is a de-
generate case, and hardware is not required to detect this
DS97KEY2005
PRELIMINARY
31