Z8E520 Datasheet, PDF (25/43 Pages) Zilog, Inc. – 1.5 MBPS USB Device Controller

Zilog
Z8E520/C520
1.5 MBPS USB Device Controller
HIGH PRIORITY INTR: This register contains the IRQ s SETUP EP1: This bit is set after the completion of the
source flags of a high-priority communications interrupt.
setup stage of a control transfer on EP1. This bit is valid
The ISR should check these bits to determine the cause of
the interrupt. Writing a 1 to their position clears interrupt
only in EP mode 011.
1
sources. Read/Write.
s SETUP EP0: This bit is set after the completion of the
setup stage of a control transfer on EP0.
s RESUME: This bit is set when the ACTIVITY bit is set in
the USB CSR, allowing the device to wake up on any
activity of the USB.
s STALL SENT EP2: This bit is set when a STALL is sent
on EP2. This bit is valid only in EP modes 100, 101, 110
HIGH PRIORITY MASK: This register contains mask bits
for the IRQ sources specified in the HIGH PRIORITY INTR
register. A set bit indicates that the corresponding interrupt
source is unmasked.
and 111.
EP0 CSR: Control/Status register of Endpoint 0 (Control
s STALL SENT EP1: This bit is set when a STALL is sent
on EP1. This bit is not valid in EP mode 000.
s STALL SENT EP0: This bit is set when a STALL is sent
on EP0.
pipe).
EP1/2 CSR: Control/Status register of additional end-
points. The definition of these bits depends on the EP
Mode as specified in the USB CSR. Read/Write.
Table 11 illustrates the EP1/2 CSR registers according to
EP Mode:
Table 11. EP 1/2 CSR Registers (BA)
EP
MODE
Description
000 EP1 OFF, EP2 OFF
FORCE
STALL
001 EP1 IN EP2 OFF
FORCE
STALL
010 EP1 OUT, EP2 OFF
FORCE
STALL
011 EP1 CONTROL
ACK SETUP OUT
OUT FORCE
STATUS BUFFER SERVICED DATA STALL
OUT VOLATILE
TOGGLE
100 EP1 OUT, EP2 OUT FORCE FORCE OUT
OUT FORCE
STALL NAK SERVICED DATA STALL
TOGGLE
101 EP1 IN, EP1 OUT
FORCE FORCE OUT
OUT FORCE
STALL NAK SERVICED DATA STALL
TOGGLE
110 EP1 OUT, EP1 IN
FORCE
STALL
FORCE
NAK
IN
IN
FORCE
PACKET DATA STALL
READY TOGGLE
111 EP1 IN EP2 IN
FORCE
STALL
FORCE
NAK
IN
IN
FORCE
PACKET DATA STALL
READY TOGGLE
EP 1
FORCE
NAK
FORCE
NAK
FORCE
NAK
FORCE
NAK
FORCE
NAK
FORCE
NAK
FORCE
NAK
FORCE
NAK
IN
PACKET
READY
IN
PACKET
READY
OUT
PACKET
READY
IN
PACKET
READY
OUT
PACKET
READY
IN
PACKET
READY
OUT
PACKET
READY
IN
PACKET
READY
IN
DATA
TOGGLE
IN
DATA
TOGGLE
OUT
DATA
TOGGLE
IN
DATA
TOGGLE
OUT
DATA
TOGGLE
IN
DATA
TOGGLE
OUT
DATA
TOGGLE
IN
DATA
TOGGLE
FORCE STALL: Forces the SIE to stall all IN and OUT
transactions. The successful receipt of a setup token
clears this bit. STALL takes priority over NAK or ACK.
Read/Write.
IN PACKET READY: When clear, IN transactions are
NAK’d. This bit cannot be cleared by firmware. To clear it,
firmware should be set FORCE NAK. Firmware must not
write to the IN buffer or IN COUNT while this bit is set. It is
cleared when the SIE sets IN DONE or when the SIE re-
DS97KEY2005
PRELIMINARY
25