Z8E520 Datasheet, PDF (3/43 Pages) Zilog, Inc. – 1.5 MBPS USB Device Controller

Zilog
Z8E520/C520
1.5 MBPS USB Device Controller
COMMUNICATION MODES
The Z8E520/C520 allows its user to function in a variety of GPIO Mode. In General-Purpose I/O Mode, the serial
1 ^{communication modes. Having this freedom within a sin- communications pins function as standard I/O pins, with}
gle chip opens up many possibilities when utilizing multiple Input, Output P/P (Push/Pull) and OD (Open Drain) Out-
protocol applications. The modes incorporated into the put.
Z8E520/C520 include PS/2, RS232, GPIO, and USB. A
description of each mode is detailed below.
USB Mode. The Z8E520 includes two bidirectional end-
points that support communications compliant to the USB
PS/2 Mode. The serial baud rate is fixed at 12.5 K baud. Specification version 1.0. The serial communications pins
Received data is automatically checked for parity and function as D– (PB6) and D+ (PB7). The detailed behavior
framing errors while HOST abort is supported. The serial of the SIE is controllable by the firmware, and three sepa-
communications pins function as PS/2 compatible DATA rate power states are provided for USB Suspend Mode
(PB6) and CLOCK (PB7).
support (see section below).
RS232 Mode. The data rate is fixed at 1200 baud. The se-
rial communications pins function as RxD (PB6) and TxD
(PB7).
USB SUSPEND/RESUME FUNCTIONALITY
Suspend is dedicated through firmware by timing the Ac-
tivity bit which is set by the SIE.
In Stop Mode, with the WDT disabled, power requirements
are minimized. No power is consumed by the voltage reg-
ulator, the Z8^Plus core, nor differential detector. Only the
Stop Mode Recovery (SMR) is enabled, so an input signal
or Resume from the host can be detected and used to
wake up the microcontroller.
In Stop Mode, with the WDT enabled, slightly more power
is consumed, but the device can wake up periodically to
perform maintenance and detect a change of state in the
application.
USB FUNCTIONAL BLOCK DESCRIPTION
The USB portion of the chip is divided into two areas, the
transceiver and the Serial Interface Engine (SIE). The
transceiver handles incoming differential signals and “sin-
gle ended zero (SE0)”. It also converts output data in digi-
tal form to differential drive at the proper levels (Figure 2).
The SIE performs all other processing on incoming and out
going data, including signal recovery timing, bit stuffing,
validity checking, data sequencing, and handshaking to
the host. Data flow into and out of the MCU portions are
dedicated registers mapped into Expanded Register File
Memory.
The USB SIE handles three endpoints (control at Endpoint
0, data into the host from Endpoint 1 and data out from the
host as Endpoint 2). All communications are at the
1.5 MB/sec data rate. Endpoint 1 and 2 can be combined
as Control EP1.
Figure 2. Data To/From Z8E520/C520
DS97KEY2005
PRELIMINARY
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