Z86E04 Datasheet, PDF (33/44 Pages) Zilog, Inc. – CMOS Z8 OTP MICROCONTROLLERS

Zilog
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Low EMI Emission
ROM Protect. ROM Protect fully protects the Z8 ROM
The Z8 can be programmed to operate in a low EMI Emis-
sion (Low Noise) Mode by means of an EPROM program-
mable bit option. Use of this feature results in:
code from being read externally. When ROM Protect is se-
lected, the instructions LDC and LDCI are supported
(Z86E04/E08 and Z86C04/C08 do not support the instruc-
tions of LDE and LDEI). When the device is programmed
1
s Less than 1 mA consumed during HALT Mode.
for ROM Protect, the Low Noise feature will not automati-
cally be enabled.
s All drivers slew rates reduced to 10 ns (typical).
Please note that when using the device in a noisy environ-
s Internal SCLK/TCLK = XTAL operation limited to a
maximum of 4 MHz–250 ns cycle time.
s Output drivers have resistances of 500 ohms (typical).
ment, it is suggested that the voltages on the EPM and CE
pins be clamped to V_CC through a diode to V_CC to prevent
accidentally entering the OTP Mode. The V_PP requires
both a diode and a 100 pF capacitor.
s Oscillator divide-by-two circuitry eliminated.
In addition to V_DD and GND (V_SS), the Z8 changes all its pin
functions in the EPROM Mode. XTAL2 has no function,
XTAL1 functions as CE, P31 functions as OE, P32 func-
tions as EPM, P33 functions as V_PP, and P02 functions as
PGM.
Auto Latch Disable. Auto Latch Disable option bit when
programmed will globally disable all Auto Latches.
WDT Enable. The WDT Enable option bit, when pro-
grammed, will have the hardware enabled Permanent
WDT enabled after exiting reset and can not be stopped in
Halt or Stop Mode.
EPROM/Test Mode Disable. The EPROM/Test Mode
Disable option bit, when programmed, will disable the
EPROM Mode and the Factory Test Mode. Reading, veri-
fying, and programming the Z8 will be disabled. To fully
verify that this mode is disabled, the device must be power
cycled.
User Modes. Table 7 shows the programming voltage of
each mode.
Table 7. OTP Programming Table
Programming Modes
V_PP
EPM
CE
OE
PGM
EPROM READ
NU
PROGRAM
V_H
PROGRAM VERIFY
V_H
EPROM PROTECT
V_H
LOW NOISE SELECT
V_H
AUTO LATCH DISABLE
V_H
WDT ENABLE
V_H
EPROM/TEST MODE
V_H
V_H
V_IL
V_IL
V_IH
V_IH
V_IL
V_IH
V_IL
V_IH
V_IL
V_IL
V_IH
V_H
V_H
V_IH
V_IL
V_IH
V_H
V_IH
V_IL
V_IH
V_H
V_IL
V_IL
V_IL
V_H
V_IH
V_IL
V_IL
V_H
V_IL
V_IL
Notes:
1. V_H =12.75V ± 0.25 V_DC .
2. V_IH = As per specific Z8 DC specification.
3. V_IL= As per specific Z8 DC specification.
4. X = Not used, but must be set to V_H or V_IH level.
5. NU = Not used, but must be set to either V_IH or V_IL level.
6. I_PP during programming = 40 mA maximum.
7. I_CC during programming, verify, or read = 40 mA maximum.
8. * V_CC has a tolerance of ±0.25V.
ADDR
ADDR
ADDR
ADDR
NU
NU
NU
NU
NU
DATA
Out
In
Out
NU
NU
NU
NU
NU
V_CC*
5.0V
6.4V
6.4V
6.4V
6.4V
6.4V
6.4V
6.4V
DS97Z8X1104
PRELIMINARY
33