Z86E04 Datasheet, PDF (31/44 Pages) Zilog, Inc. – CMOS Z8 OTP MICROCONTROLLERS

Zilog
Z86E04/E08
CMOS Z8 OTP Microcontrollers
HALT Mode. This instruction turns off the internal CPU Watch-Dog Timer (WDT). The Watch-Dog Timer is en-
clock but not the crystal oscillation. The counter/timers and abled by instruction WDT. When the WDT is enabled, it
1 ^{external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac- cannot be stopped by the instruction. With the WDT in-}
tive. The device is recovered by interrupts, either external- struction, the WDT is refreshed when it is enabled within
ly or internally generated. An interrupt request must be ex- every 1 Twdt period; otherwise, the controller resets itself,
ecuted (enabled) to exit HALT Mode. After the interrupt The WDT instruction affects the flags accordingly; Z=1,
service routine, the program continues from the instruction S=0, V=0.
after the HALT.
WDT = 5F (Hex)
Note: On the C12 ICEBOX, the IRQ3 does not wake the
device out of HALT Mode.
Opcode WDT (5FH). The first time Opcode 5FH is execut-
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current to 10 µA. The STOP Mode is released by a RESET
through a Stop-Mode Recovery (pin P27). A Low input
condition on P27 releases the STOP Mode. Program exe-
cution begins at location 000C(Hex). However, when P27
ed, the WDT is enabled and subsequent execution clears
the WDT counter. This must be done at least every T_WDT;
otherwise, the WDT times out and generates a reset. The
generated reset is the same as a power-on reset of T_POR,
plus 18 XTAL clock cycles. The software enabled WDT
does not run in STOP Mode.
is used to release the STOP Mode, the I/O port Mode reg-
isters are not reconfigured to their default power-on condi-
tions. This prevents any I/O, configured as output when the
STOP instruction was executed, from glitching to an un-
known state. To use the P27 release approach with STOP
Mode, use the following instruction:
Opcode WDH (4FH). When this instruction is executed it
enables the WDT during HALT. If not, the WDT stops
when entering HALT. This instruction does not clear the
counters, it just makes it possible to have the WDT running
during HALT Mode. A WDH instruction executed without
executing WDT (5FH) has no effect.
LD
NOP
STOP
P2M, #1XXX XXXXB
X = Dependent on user's application.
Note: A low level detected on P27 pin will take the device
out of STOP Mode even if configured as an output.
In order to enter STOP or HALT Mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user executes a
NOP (opcode=FFH) immediately before the appropriate
SLEEP instruction, such as:
FF
NOP
; clear the pipeline
6F
STOP
; enter STOP Mode
or
FF
NOP
; clear the pipeline
7F
HALT
; enter HALT Mode
Permanent WDT. Selecting the hardware enabled Perma-
nent WDT option, will automatically enable the WDT upon
exiting reset. The permanent WDT will always run in HALT
Mode and STOP Mode, and it cannot be disabled.
Auto Reset Voltage (V_LV). The Z8 has an auto-reset built-
in. The auto-reset circuit resets the Z8 when it detects the
V_CC below V_LV.
Figure 17 shows the Auto Reset Voltage versus tempera-
ture. If the V_CC drops below the VCC operating voltage
range, the Z8 will function down to the V_LV unless the inter-
nal clock frequency is higher than the specified maximum
V_LV frequency.
DS97Z8X1104
PRELIMINARY
31