Z86E04 Datasheet, PDF (19/44 Pages) Zilog, Inc. – CMOS Z8 OTP MICROCONTROLLERS

Zilog
Z86E04/E08
CMOS Z8 OTP Microcontrollers
LOW NOISE VERSION
Low EMI Emission
The Z86E04/E08 can be programmed to operate in a Low
s Output drivers have resistances of 500 Ohms (typical).
s Oscillator divide-by-two circuitry eliminated.
1
EMI Emission Mode by means of a mask ROM bit option.
Use of this feature results in:
The Low EMI Mode is mask-programmable to be selected
s All pre-driver slew rates reduced to 10 ns typical.
by the customer at the time the ROM code is submitted.
s Internal SCLK/TCLK operation limited to a maximum of
4 MHz–250 ns cycle time.
PIN FUNCTIONS
OTP Programming Mode
D7–D0 Data Bus. Data can be read from, or written to, the
EPROM through this data bus.
V_CC Power Supply. It is typically 5V during EPROM Read
Mode and 6.4V during the other modes (Program, Pro-
gram Verify, and so on).
CE Chip Enable (active Low). This pin is active during
EPROM Read Mode, Program Mode, and Program Verify
Mode.
OE Output Enable (active Low). This pin drives the Data
Bus direction. When this pin is Low, the Data Bus is output.
When High, the Data Bus is input.
EPM EPROM Program Mode. This pin controls the differ-
ent EPROM Program Modes by applying different
voltages.
V_PP Program Voltage. This pin supplies the program volt-
age.
Clear Clear (active High). This pin resets the internal ad-
dress counter at the High Level.
Clock Address Clock. This pin is a clock input. The internal
address counter increases by one with one clock cycle.
PGM Program Mode (active Low). A Low level at this pin
programs the data to the EPROM through the Data Bus.
Application Precaution
The production test-mode environment may be enabled
accidentally during normal operation if excessive noise
surges above V_CC occur on the XTAL1 pin.
In addition, processor operation of Z8 OTP devices may be
affected by excessive noise surges on the V_PP, CE, EPM,
OE pins while the microcontroller is in Standard Mode.
Recommendations for dampening voltage surges in both
test and OTP Mode include the following:
s Using a clamping diode to V_CC.
s Adding a capacitor to the affected pin.
Note: Programming the EPROM/Test Mode Disable
option will prevent accidental entry into EPROM Mode or
Test Mode.
DS97Z8X1104
PRELIMINARY
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