Z86E04 Datasheet, PDF (28/44 Pages) Zilog, Inc. – CMOS Z8 OTP MICROCONTROLLERS

Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has six interrupts from six different
sources. These interrupts are maskable and prioritized
(Figure 15). The sources are divided as follows: the falling
edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge
of P32 (AN2), and two counter/timers. The Interrupt Mask
Register globally or individually enables or disables the six
interrupt requests (Table 4).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an Interrupt Request
is granted. This disables all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
Note: User must select any Z86E08 mode in Zilog's C12
ICEBOX^™ emulator. The rising edge interrupt is not sup-
ported on the CCP emulator (a hardware/software
workaround must be employed).
Table 4. Interrupt Types, Sources, and Vectors
Name Source
IRQ0
IRQ1
IRQ2
IRQ3
AN2(P32)
REF(P33)
AN1(P31)
AN2(P32)
IRQ4 T0
IRQ5 T1
Notes:
F = Falling edge triggered
R = Rising edge triggered
Vector
Location Comments
0,1
2,3
4,5
6,7
8,9
10,11
External (F)Edge
External (F)Edge
External (F)Edge
External (R)Edge
Internal
Internal
IRQ0 - IRQ5
IRQ
Interrupt
Request
IMR
Global
6
Interrupt
Enable
IPR
PRIORITY
LOGIC
Vector Select
Figure 15. Interrupt Block Diagram
28
PRELIMINARY
DS97Z8X1104