MT90520 Datasheet, PDF (94/180 Pages) Zarlink Semiconductor Inc – 8-Port Primary Rate Circuit Emulation AAL1 SAR

MT90520
Data Sheet
Section 4.7.2.2, “Synchronous Clocking Circuit” may be sourced from the internal PLL clock or the TDM input clock
for any DS1/E1 port of the device.
Digital PLL
PLL_INPUT_SEL
PLLCLK
4:1
Mux
Adaptive Mode
8 kHz Network Mode
SRTS Mode
Line Clocking Mode
SDT/UDT Interface (one
per port)
TDM
Bus
Module
STiCLK
LOS
...
16:2
Mux
common TDM rate clock
MCLK/2
4:1
Mux
SToCLK
CLKSEL
External
PLL
EXT/INT
PRI_REF
2:1
TDM_CLK ^Mux
SLV/MSTR
2:1
Mux
/512 or /256
C4M/C2M
F0_MODE<2>
Backplane
Interface and
Common Clock
Generation (one
per device)
F0_MODE
<1:0>
Convert to
External
Format
SLV/MSTR
2:1 ^F0
Mux
C4M_C2M_
in
C4M_C2M_
out
F0_out F0_in
Note1: Shaded sections of figure above indicate circuitry outlined elsewhere in this document.
Note2: The SDT/UDT interface is replicated on a per-port basis. The backplane interface and common clock generation circuitry are only implemented once
per device.
Figure 34 - Interface to TDM Bus Module and Common Clock Generation Circuitry
94
Zarlink Semiconductor Inc.