MT90520 Datasheet, PDF (156/180 Pages) Zarlink Semiconductor Inc – 8-Port Primary Rate Circuit Emulation AAL1 SAR

MT90520
Data Sheet
Characteristic
Sym.
Min.
Typ.
Max. Units
Test Conditions
Output Delay - MCLK rising to
t_OD
(MEM_ADD[19:0], MEM_DATA[17:0]) VALID
and (MEM_CS_X and MEM_WR) asserted
12.5
ns C_L = 35 pF
Output Hold Time - MCLK rising
MEM_DATA[17:0] INVALID
t_OH
1
ns C_L = 35 pF
High-Z to Drive Time - MCLK rising to
MEM_DATA[17:0] driven
t_ZD
3
ns C_L = 35 pF
Clock to Change - MCLK rising to
t_OC
1
(MEM_ADD[19:0], MEM_CS_X and MEM_WR)
change
ns C_L = 35 pF
Drive to High-Z Time - MCLK rising to
MEM_DATA[17:0] High-Z
t_DZ
1
6.5
ns C_L = 35 pF
Table 93 - External Memory Interface Timing - Write Cycle Parameters
MCLK
MEM_ADD[19:0]
MEM_CS_X
MEM_WR
MEM_DATA[17:0]
(flow-through)
MEM_DATA[17:0]
(pipelined)
t_MP
t_MH
t_ML
ADDRESS VALID
t_OD
t_OC
t_OC
t_OD
t_OC
t_DZ
DATA VALID
t_ZD
t_OH
t_OD
DATA VALID
Figure 52 - External Memory Interface Timing - Write Cycle
V_TT
V_TT
V_TT
V_TT
V_TT
V_TT
156
Zarlink Semiconductor Inc.