MT90520 Datasheet, PDF (138/180 Pages) Zarlink Semiconductor Inc – 8-Port Primary Rate Circuit Emulation AAL1 SAR

MT90520
Data Sheet
Address: 5002 (Hex)
Label: PLLCS
Reset Value: 0000 (Hex)
Label
PRI_SEL
Bit
Position
5:0
SEC_SEL
11:6
Reserved
15:12
Type
Description
R/W Primary Clock Source for External PLL.
Used to select the primary clock source for the external PLL (signals output on PRI_REF
and PRI_LOS).
Bits<4:0> indicate which port should provide the clock source (only “00000”:“00111”
are valid choices).
Bit<5> indicates whether the port’s TDM input clock (STiCLK) or the port’s internally-
generated PLL clock should be used as the clock source. ‘0’ = STiCLK; ‘1’ = PLLCLK.
Note: If the port selected to provide the primary reference experiences an LOS condition,
that port’s PLLCLK will be used as PRI_REF, even if the port’s STiCLK is selected via
PRI_SEL<5>.
R/W Secondary Clock Source for External PLL.
Used to select the secondary clock source for the external PLL (signals output on
SEC_REF and SEC_LOS).
Bits<4:0> indicate which port should provide the clock source (only “00000”: “00111”
are valid choices).
Bit<5> indicates whether the port’s TDM input clock (STiCLK) or the port’s internally-
generated PLL clock should be used as the clock source. ‘0’ = STiCLK; ‘1’ = PLLCLK.
Note: An LOS condition on the port selected to provide the secondary reference clock will
have no effect on the selection of the clock source for SEC_REF.
R/O Always reads “0000”.
Table 74 - External PLL Clock Source Register
138
Zarlink Semiconductor Inc.