MT90520 Datasheet, PDF (158/180 Pages) Zarlink Semiconductor Inc – 8-Port Primary Rate Circuit Emulation AAL1 SAR

MT90520
Data Sheet
Characteristic
Sym.
Min.
Typ.
Max. Units
STiCLK/C4M/C2M Clock Period
t_STiCK
1.544 Mbps bus (1.544 MHz clock)
648
ns
1.544 or 2.048 Mbps bus (2.048 MHz clock)
488
ns
2.048 Mbps bus (4.096 MHz clock)
244
ns
STiCLK/C4M/C2M Pulse Width (HIGH / LOW)
t_STiCKH/L
1.544 Mbps bus (1.544 MHz clock)
324
ns
1.544 or 2.048 Mbps bus (2.048 MHz clock)
244
ns
2.048 Mbps bus (4.096 MHz clock)
122
ns
Frame Pulse Width
1.544 Mbps (Generic)
2.048 Mbps (Generic)
2.048 Mbps (ST-BUS)
t_FPW
100
648
900
ns
100
488
600
ns
100
244
300
ns
Frame Pulse Setup Time
t_FIS
STiMF/F0 valid to STiCLK/C4M/C2M rising
15
ns
STiMF/F0 valid to STiCLK/C4M/C2M falling
15
ns
Frame Pulse Hold Time
t_FIH
STiCLK/C4M/C2M rising to STiMF/F0 invalid
10
ns
STiCLK/C4M/C2M falling to STiMF/F0 invalid
10
ns
Table 94 - TDM Bus Input Clock Parameters
Test Conditions
Characteristic
Sym. Min. Typ. Max.
Data Setup Time - DSTi/CSTi VALID to STiCLK/C4M/C2M falling
Sampling on falling edge
t_SIS
15
Data Hold Time - STiCLK/C4M/C2M falling to DSTi/CSTi INVALID
t_SIH
10
Sampling on falling edge
Data Setup Time - DSTi/CSTi VALID to STiCLK/C4M/C2M rising
Sampling on rising edge
t_SIS
15
Data Hold Time - STiCLK/C4M/C2M rising to DSTi/CSTi INVALID
Sampling on rising edge
t_SIH
10
Table 95 - TDM Bus Input Data Parameters
Units
ns
ns
ns
ns
Test Conditions
158
Zarlink Semiconductor Inc.