MT90520 Datasheet, PDF (106/180 Pages) Zarlink Semiconductor Inc – 8-Port Primary Rate Circuit Emulation AAL1 SAR

MT90520
Data Sheet
The range of the phase detector is therefore based upon the wander tolerance at 0.1 Hz and will be 32 UI peak-to-
peak (+/- 16 UI).
Clock ^{A0 [UI}pp^{] A1 [UI}pp^] F0 [Hz] F1 [Hz] @ 0.1 Hz
C1M5
28
5
1.2E-5
10
6.2
C2M
37
18
1.2E-5
20
23
Table 22 - Minimum Input Wander and Jitter Tolerance
The maximum intrinsic output jitter allowed on the output of the PLL is specified in ITU-T G.823/G.824 and is listed
in Table 23. That said, the PLL within the MT90520 has a maximum intrinsic output jitter of one half of an MCLK
cycle. However, any jitter on MCLK will be directly transferred to the output clocks.
Clock
A [UI_pp]
A [ns]
C1M5
0.1
65
C2M
0.2
98
Table 23 - Maximum Allowed Intrinsic Output Jitter
MTIE (Maximum Time Interval Error)
ANSI T1.403 and T1.101 require that the output phase change at a speed of no more than 81 ns per 1.326 ms, with
a maximum phase change of 1 µs. Therefore, the slew rate of the DCO input is no more than 61 ppm of the center
frequency setting. The “no more than 81 ns / 1.326 ms” requirement is met in all modes.
Since the period of the 1.544 MHz, 2.048 MHz, and 4.096 MHz signals is less than 1 µs, that requirement is met
automatically when the PLL is in synchronous mode. When switching between modes, the 1 µs MTIE is not
guaranteed.
Locking Range
When using an 8 kHz, 2.048 MHz, or 4.096 MHz input clock, a locking range of + 246 ppm is provided. When the
input clock is 1.544 MHz, the locking range is +245 ppm. Note that the locking range is related to the master clock.
If the master clock (i.e., MCLK) is 100 ppm too low, the whole locking range also shifts 100 ppm downwards.
4.8 Test Interface
The MT90520 contains an IEEE 1149 standard Test Access Port (TAP), which provides Boundary-Scan test access
to aid board-level testing. (IEEE 1149 is often referred to by its older designation: JTAG - Joint Test Action Group.)
4.8.1 Test Access Port
The test port is a standard IEEE 1149 interface, with the optional TRST pin. The Test Access Port consists of 5 pins:
TCK: Boundary-scan Test Clock.
TDI: Test Data In; input pin clocked in on the rising edge of TCK. TDI should be pulled HIGH if bound-
ary-scan is not in use.
TDO: Test Data Out; output pin updated on the falling edge of TCK. The output is in high-impedance
except when data is actually being shifted out.
TMS: Test Mode Select; input control line clocked in on the rising edge of TCK. TMS should be pulled
HIGH if boundary-scan is not in use.
106
Zarlink Semiconductor Inc.