MT90520 Datasheet, PDF (142/180 Pages) Zarlink Semiconductor Inc – 8-Port Primary Rate Circuit Emulation AAL1 SAR

6.2.9 TDM Interface Module
MT90520
Data Sheet
Address: 6000 (Hex)
Label: MAINTDM1
Reset Value: FFFF (Hex)
Label
Bit Position
IDLE_DATA
7:0
SILENCE_DATA
15:8
Type
Description
R/W User-programmable idle data. (Applies only to SDT mode.)
When a channel is idle (I bit is set in the corresponding TDM SDT Reassembly Control
Structure), idle data is output on DSTo.
R/W User-programmable silence data. (Applies only to SDT mode.)
When a channel is experiencing a TDM underrun, this silence data is output on DSTo if
REPLAY_N_SILENCE is cleared in the TDM Control Register 3 for that port.
Table 80 - Main TDM Control Register 1
Address: 6002 (Hex)
Label: MAINTDM2
Reset Value: F000(Hex)
Label
Reserved
IDLE_CAS
Bit Position
11:0
15:12
Type
Description
R/O Always reads “0000_0000_0000”.
R/W User-programmable idle CAS. (Applies only to SDT mode.)
When a channel is idle (I bit is set in the corresponding TDM SDT Reassembly Control
Structure), idle CAS nibbles are output on CSTo.
Table 81 - Main TDM Control Register 2
Address: 6200 + p*10 (Hex)
Label: TDM1_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
Label
TDM_CIR_BUF_
LPBK
Bit
Position
0
TDM_LOS_CLK
1
TDM_LOS_POL
2
TDM_CAS_
3
LOCATION
TDM_MAPPING_
4
SCH
Type
R/W
R/W
R/W
R/W
R/W
Description
TDM Circular Buffer Loopback. (Applies only to SDT mode.)
‘0’ = Normal operation.
‘1’ = Data input on DSTi is output on DSTo, after routing through the SDT circular buffers in
external memory.
Incoming Loss of Signal. (Applies only to UDT mode.)
‘0’ = Normal operation (continue to use STiCLK during an LOS condition).
‘1’ = Switch to MT90520’s internal clock source if loss of signal is detected on CSTi/LOSi.
Incoming TDM LOS Polarity. (Applies only to UDT mode; must be set in SDT mode.)
‘0’ = Negative polarity (i.e., zero on CSTi/LOSi means loss of signal).
‘1’ = Positive polarity (i.e., one on CSTi/LOSi means loss of signal).
TDM Signalling. (Applies only to SDT mode.)
‘0’ = Signalling nibbles are located in the LS four bits of each channel.
‘1’ = Signalling nibbles are located in the MS four bits of each channel.
TDM Mapping Scheme. (Applies only to an incoming DS1 link in SDT mode.)
In Generic mode:
‘0’ = Use first 24 channels.
‘1’ = Use 3 channels out of every 4.
In ST-BUS mode, this bit must be cleared.
Table 82 - TDM Control Register 1 (one per port)
142
Zarlink Semiconductor Inc.