MT90520 Datasheet, PDF (91/180 Pages) Zarlink Semiconductor Inc – 8-Port Primary Rate Circuit Emulation AAL1 SAR

MT90520
Data Sheet
incoming ATM cells by the UDT RX_SAR or SDT RX_SAR are input to the Clock Management module. Within this
module, the RTS values are compared with the network clock and a new line-rate clock is generated by an internal
PLL. This clock may be sent directly to the TDM bus module for use as a TDM output clock or it may be used as a
reference clock for an external PLL.
Adaptive clock recovery is performed by the Clock Management module on a per-port basis, based on the fill level
of the Reassembly Circular Buffers.
An overview of the functionality of the Clock Management module is given in Figure 32.
Clock Management Module
Clock Control
Clock Recovery
Clock Selection
and Frame Pulse
Generation
SRTS
LOS Clock
Generation
UDT
SDT
Transmit
Synchronous
Adaptive
External
PLL
Internal
PLL
SRTS
Receive
Framer
TDM
Backplane
Network
Clock
Plesiochronous
Figure 32 - Functions of the Clock Management Module
At a high level of abstraction, Figure 33 gives a general overview of the interaction between the Clock Management
module and other modules within the MT90520 device. The internal configuration of the Clock Management
module is examined more fully in the subsequent sub-module descriptions.
91
Zarlink Semiconductor Inc.