MT90502_06 Datasheet, PDF (89/205 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Data Sheet
Address
Bits
[5]
[6]
[12:8]
[13]
[14]
746h
[4:0]
[5]
[6]
[12:8]
[13]
[14]
748h
[4:0]
[5]
[6]
[12:8]
[13]
[14]
802h
[1]
[2]
804h
[1]
[2]
820h
[8:0]
822h
824h
828h
[11:9]
[13:0]
[13:0]
[8:0]
82Ah
82Ch
[11:9]
[13:0]
[13:0]
Register
Bits
Description
gpio_4_output_constant Constant value of ‘00110’ (of Table 32)
gpio_4_output_enable
‘0’ - tri-state, ‘1’ - output enabled.
gpio_5_output_select
See Table 32, “GPIO mux, Output Selection,” on
page 90.
gpio_5_output_constant Constant value of ‘00110’ (See Table 32 - on page 90).
gpio_5_output_enable
‘0’ - tri-state, ‘1’ - output enabled.
gpio_out_reg3
gpio_6_output_select
See Table 32, “GPIO mux, Output Selection,” on
page 90.
gpio_6_output_constant
Constant value of ‘00110’ (see Table 32, “GPIO mux,
Output Selection,” on page 90).
gpio_6_output_enable
‘0’ - tri-state, ‘1’ - output enabled.
gpio_7_output_select
See Table 32, “GPIO mux, Output Selection,” on
page 90.
gpio_7_output_constant Constant value of ‘00110’ (of Table 32)
gpio_7_output_enable
‘0’ - tri-state, ‘1’ - output enabled.
gpio_out_reg4
ct_netref1_output_select
See Table 32, “GPIO mux, Output Selection,” on
page 90.
ct_neterf1_output_constant Constant value of ‘00110’ (See Table 32, “GPIO mux,
Output Selection,” on page 90).
ct_netref1_output_enable ‘0’ - tri-state, ‘1’ - output enabled.
ct_netref2_output_select
See Table 32, “GPIO mux, Output Selection,” on
page 90.
ct_netref2_output_constant Constant value of ‘00110’ (of Table 32)
ct_netref2_output_enable ‘0’ - tri-state, ‘1’ - output enabled.
status0
pointa_buf_overflow
Overflow occurred in the point A buffer.
pointb_buf_overflow
Overflow occurred in the point B buffer.
satus0_ie
pointa_buf_overflow
If ‘1’, pointa_buf_overflow will generate interrupt.
pointb_buf_overflow
If ‘1’, pointb_buf_overflow will generate interrupt.
pointa_manage
pointa_buffer_base_add
Bits 20:12 of the base address of the clock recovery
point buffer.
pointa_buffer_size
see Table 31
pointa_read
pointa_rpnt
CPU’s read pointer to the clock recovery point FIFO.
pointa_write
pointa_wont
Chip’s write pointer to the clock recovery point FIFO.
pointb_manage
pointb_buffer_base_add
Bits 20:12 of the base address of the clock recovery
point buffer.
pointb_buffer_size
See Table 31, “Buffer Sizes,” on page 90.
pointb_read
pointb_rpnt
CPU’s read pointer to the clock recovery point FIFO.
pointb_write
pointb_wont
Chip’s write pointer to the clock recovery point FIFO.
Table 30 - Clock Recovery Registers (continued)
89
Zarlink Semiconductor Inc.