MT90502_06 Datasheet, PDF (51/205 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Data Sheet
2.3.3 AAL0 Cells
The TX SAR has the ability to insert AAL0 cells in the transmission direction. AAL0 cells are generated by the CPU
and are directed to a 4-cell internal FIFO memory. It is necessary for the CPU to read the AAL0_MONITOR register
(310h) to ascertain if the 4-cell internal FIFO memory can accommodated the pending AAL0 cell. The destination of
the AAL0 cell is determined by the TX Destination field.
The aal0_input_fifo is 4 cells deep in the MT90502, however, it is the hardware that manages the pointers. The
software will write the cell to the first entry (0x2100 to 0x213E) and then it will set the register indicating that there is
a new cell. There is more than 1 cell to write at a time and the aal0_input_cell_written is set after each cell.
2.4 RX SAR
The RX SAR module performs processing on ATM cells received from the UTOPIA module. Cells placed in the RX
SAR Output FIFO by the UTOPIA module are first read, then divided into the component CPS-Packets, and finally
written into the appropriate CPS-Packet data circular buffer in external memory. The processing involves
• identifying the VC corresponding to the cell
• examining the cell for errors
• determining the routing of each CID, and
• disassembling the cell’s CPS-Packets.
The status of the circular buffers is monitored for underruns and overruns. The RX SAR module also directs data
cells to the data cell FIFO from which the CPU can read them. The RX SAR module supports PCM and ADPCM
CPS-Packets of 1, 2, 3, 4, 5, or 8 EDUs, 32K ADPCM 80 frame CPS-Packets, 32K ADPCM 88 frame CPS-Packets,
PCM 44 frame CPS-Packets, HDLC CPS-Packets of 1 to 64-bytes in length, and can accommodate packets
straddling multiple cells.
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Zarlink Semiconductor Inc.