MT90502_06 Datasheet, PDF (182/205 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Data Sheet
Address: 904h
Label: status0_ie
Reset Value: 0000h
Label
Bit
Position
Type
Description
llman_process_crashed_ie
0
underrun_detect_ie
1
underrun_wrap_detect_ie
2
rxtdm_read_cache_overflow_ie
3
rxtdm_write_cache_overflow_ie
4
write_back_cache_overflow_ie
5
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
rx_tdm_fifo_overflow_ie
rxsar_pointer_wb_overflow_ie
reserved
6
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
7
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
15:8 RO Reserved. Always read as “0000_0000”
Table 200 - RX TDM Interrupt Enable Register 0
Address: 908h
Label: monitor
Reset Value: 0000h
Label
Bit Position Type
Description
hdlc_pcm_channel_error 9:0
RO Indicates the channel number, according to its position in the RX
TDM control memory, on which the last underrun or underrun wrap
error occurred
reserved
15:10 RO Reserved. Always read as “0000_00”
Table 201 - RX TDM Channel Number Monitor Register
182
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