MT90502_06 Datasheet, PDF (115/205 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Data Sheet
Address: 104h
Label: status0_ie
Reset Value: 0000h
Label
Bit Position Type
Description
reserved
internal_read_timeout_ie
cpu_read_done_ie
reserved
2:0
RO Reserved. Always read as “000”
3
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
4
IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
15:5
RO Reserved. Always read as “0000_0000_000”
Table 37 - CPU Interrupt Enable Register
Address: 108h
Label: mem_clk_freq
Reset Value: 0000h
Label
Bit Position Type
Description
reserved
mem_clk_freq_integer
reserved
3:0
10:4
15:11
RO Reserved
RW Frequency of mem_clk in MHz.
RW Reserved. Must always be “0000”
Table 38 - Mem_clk Frequency Control Register
Address: 10Ah
Label: upclk_freq
Reset Value: 0000h
Label
reserved
upclk_freq_integer
reserved
Bit Position Type
Description
3:0
10:4
15:11
RO Reserved
RW Frequency of upclk in MHz.
RW Reserved. Must always be “0000”
Table 39 - Upclk Frequency Control Register
115
Zarlink Semiconductor Inc.