MT90502_06 Datasheet, PDF (166/205 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Data Sheet
Address: 710h
Label: adapa0
Reset Value: 0001h
Label
Bit
Position ^Type
Description
Adapa_clk_divisor_reset
10
Adapa_source
12:11
adapa_clk_divisor_load_now 13
Reserved
15:14
RW When '0', this will force the Adaptive module A's clock divisor to
reset.
RW “00” = clkrecov_pulse_a; “01” = gpio[0] (any change); “10” =
gpio[0] (rising edge); “11” = gpio[0] (falling edge).
PUL When written to '1', this will allow the new div_integer and
div_fraction to be used.
PUL Reserved. Always read as “00”
Table 167 - Adaptive Module A Register 0
Address: 712h
Label: adapa1
Reset Value: 0002h
Label
adapa_div_integer
Address: 714h
Label: adapa2
Reset Value: 0000h
Label
Adapa_div_fraction
Bit Position Type
Description
15:0
RW Adaptive module A's mem_clk divisor (integer part). Range 2
to FFFFh.
Table 168 - Adaptive Module A Register 1
Bit Position Type
Description
15:0
RW Adaptive module A's mem_clk divisor (fractional part). Range 0
to FFFFh.
Table 169 - Adaptive Module A Register 2
166
Zarlink Semiconductor Inc.