MT90502_06 Datasheet, PDF (84/205 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Data Sheet
Adaptive Clock Re cov ery Event Information
b 15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
+0
m_mem_em__{_}c_clk_lk__{_}c_io_{_c}u_on_ute_nr_t[_e3_r1_[3:1_:6₁]_6]
+2
memmem_c_lckl_kc_oi_ucnotuenrt[e1r5[:105]:0 ]
+4
ref_counter[31 :16]
+6
ref_counter[15 :0]
+8
mem_clk_i_cycles_since_last_ ref_i ncrement[15:0]
+A
LI[5:0]
UUI[4:0]
+C
+E
mem_ clk_i_counter : Freerunning mem_clk_i cycle counter. This field is used as a reli able
time-stamp in the clock recovery algori thm.
re f_counte r : Freerunning reference clock cycle counter. This field is used to control wa nder
in the generation of the reference clock.
mem_ clk_i_cycle s_since_last_ ref_increment
: This field counts the number of mem_clk_i
cycles since the last ti me the ref_counter i ncremented. This field is used to control wander in
the generatio n of the reference clock.
LI & UUI : Length and UUI information o f the m_Ci_Pni_S-_-p_Pa_ac_ck_ke_et_tthat generated this clock recove ry
event information structure .
clk1.cdd
Re served
Figure 46 - Adaptive Clock Recovery Event Information
The base addresses and structures sizes for adaptive clock recovery event structures for module A and module B
are programmable in registers 820h ‘pointa_manage’ and 828h ‘pointb_manage’ respectively. The address of the
structures to be read can be determined using the read and write pointers located in registers 822h ‘pointa_read’,
824h ‘pointa_write’, 82Ah ‘pointb_read’ and 82Ch ‘pointb_write’.
Similar to the event/error FIFO and the data cell FIFO, the read pointers must be updated by the CPU/software and
the write pointers are updated by the hardware.
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