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XPLA3 Datasheet, PDF (9/11 Pages) Xilinx, Inc – Excellent pin retention during design changes
CoolRunner™ XPLA3 CPLD
Terminations
The CoolRunner XPLA3 CPLDs are TotalCMOS devices.
As with other CMOS devices, it is important to consider
how to properly terminate unused inputs and I/O pins when
fabricating a PC board. Allowing unused inputs and I/O
pins to float can cause the voltage to be in the linear region
of the CMOS input structures, which can increase the
power consumption of the device. The XPLA3 CPLDs have
programmable on-chip weak pull-up resistors on each I/O
pin. These resistors are automatically activated by fitter
software for all unused I/O pins. Note that an I/O macrocell
used as buried logic that does not have the I/O pin used for
input is considered to be unused, and the weak pull-up
resistors will be turned on. It is recommended that any
unused I/O pins on the XPLA3 family of CPLDs be left
unconnected. As with all CMOS devices, do not allow
inputs to float.
R
JTAG and ISP Interfacing
A number of industry-established methods exist for
JTAG/ISP interfacing with CPLDs and other integrated
circuits. The XPLA3 family supports the following methods:
• Xilinx HW 130
• PC Parallel Port
• Workstation or PC Serial Port
• Embedded Processor
• Automated Test Equipment
• Third Party Programmers
• Xilinx ISP Programming Tools
For more details on JTAG and ISP, refer to the related
application note: JTAG and ISP in Xilinx CPLDs. see also
Table 4 below:
Table 4: Programming Specifications
Symbol
DC Parameters
VCCP
VCC supply program/verify
Parameter
ICCP
ICC limit program/verify
VIH
Input voltage (High)
VIL
Input voltage (Low)
VOL
Output voltage (Low)
VOH
Output voltage (High)
AC Parameters
FMAX
PWE
PWP
PWV
TINIT
TMS_SU
TDI_SU
TMS_H
TDI_H
TDO_CO
TCK maximum frequency
Pulse width erase
Pulse width program
Pulse width verify
Initialization time
TMS setup time before TCK ↑
TDI setup time before TCK ↑
TMS hold time after TCK ↑
TDI hold time after TCK ↑
TDO valid after TCK ↓
Min.
Max.
3.0 (com)
3.6
2.7 (ind)
80
2.0
0.8
0.4
2.4
10
100
10
10
50
10
10
20
20
30
Unit
V
mA
V
V
V
V
MHz
ms
ms
µs
µs
ns
ns
ns
ns
ns
9
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DS012 (v1.1) March 3, 2000
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