XPLA3 Datasheet, PDF (5/11 Pages) Xilinx, Inc – Excellent pin retention during design changes

R
CoolRunner™ XPLA3 CPLD
From PT Array
1
48
VFM
PLA OR Term
CT4
P-term
Universal PST
CT [0:5]
To ZIA
To ZIA
PAD
PST
D/T/L _Q
CLKEn
RST
To I/O
Global CLK
Global CLK
Universal CLK
P-term CLK
CT [4:7]
Universal RST
CT [0:5]
Note: Global CLK signals come from pins.
Figure 5: XPLA3 Macrocell Architecture
I/O Cell
The OE (Output Enable) multiplexer has eight possible
modes (Figure 6), including a programmable weak pull-up
(WPU) eliminating the need for external termination on
unused I/Os.
The I/O Cell is 5V tolerant, and has a single-bit slew-rate
control for reducing EMI generation.
Outputs are 3.3V PCI electrical specification compatible
(no internal clamp diode).
To Macrocell / ZIA
From Macrocell
GND
CT ⁴
Universal OE
V_CC
GND (Weak P.U.)
3
OE [2:0]
Figure 6: I/O Cell
ds012_05_122299
V_CC
WP ^{Weak Pull-up}
OE = 7
I/O Pin
Slew
Control
OE
Decode
0
1
2
3
4
5
6
7
I/O Pin
State
3-State
Function CT0
Function CT1
Function CT2
Function CT6
Universal OE
Enable
Weak P.U.
ds012_06_121699
5
www.xilinx.com
DS012 (v1.1) March 3, 2000
1-800-255-7778