XPLA3 Datasheet, PDF (6/11 Pages) Xilinx, Inc – Excellent pin retention during design changes

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Simple Timing Model
Figure 7 shows the XPLA3 timing model which has three
main timing parameters, including T_PD, T_SU, and T_CO. In
other architectures, the user may be able to fit the design
into the CPLD, but may not be sure whether system timing
requirements can be met until after the design has been fit
into the device. This is because the timing models of other
architectures are very complex and include such things as
timing dependencies on the number of parallel expanders
borrowed, sharable expanders, varying number of X and Y
routing channels used, etc. In the XPLA3 architecture, the
CoolRunner™ XPLA3 CPLD
user knows up front whether the design will meet system
timing requirements. This is due to the simplicity of the tim-
ing model.
Slew Rate Control
XPLA3 devices have slew rate control for each macrocell
output pin. The user has the option to enable the slew rate
control to reduce EMI. The nominal delay for using this
option is 2.0 ns.
Using Combinatorial Logic:
Input Pin
Using Register Logic:
Input Pin
or Feedback
TSUF
Clock Pin
TPD
DQ
Using Macrocell Register
as Input Register:
Input Pin
TSUF
Clock Pin
DQ
Figure 7: XPLA3 Timing Model
TCO
TF
TF
Output Pin
Output Pin
Feedback to ZIA
Feedback to ZIA
ds012_07_030300
DS012 (v1.1) March 3, 2000
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