XPLA3 Datasheet, PDF (8/11 Pages) Xilinx, Inc – Excellent pin retention during design changes

R
CoolRunner™ XPLA3 CPLD
Table 2: JTAG Pin Description
Pin
TCK
TMS
TDI
TDO
Name
Test Clock Input
Test Mode Select
Test Data Input
Test Data Output
Description
Clock pin to shift the serial data and instructions in and out of the
TDI and TDO pins, respectively.
Serial input pin selects the JTAG instruction mode. TMS should be
driven high during user mode operation.
Serial input pin for instructions and test data. Data is shifted in on
the rising edge of TCK.
Serial output pin for instructions and test data. Data is shifted out on
the falling edge of TCK. The signal is 3-stated if data is not being
shifted out of the device.
3V, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
• Design
- Faster time-to-market
- Debug partitioning and simplified prototyping
- Printed circuit board reconfiguration during debug
- Better device and board level testing
• Manufacturing
- Multi-functional hardware
- Reconfigurability for Test
Table 3: Low -level ISP Commands
- Eliminates handling of "fine lead-pitch" components
for programming
• Field Support
- Easy remote upgrades and repair
- Support for field configuration, reconfiguration, and
customization
XPLA3 allows for 3V, in-system programming/reprogram-
ming of its EEPROM cells via a JTAG interface. An on-chip
charge pump eliminates the need for externally provided
super-voltages. This allows programming on the circuit
board using only the 3V supply required by the device for
normal operation. The ISP commands implemented in
XPLA3 are specified in Table 3.
Instruction
(Register Used)
Enable
(ISP Shift Register)
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
Disable
(ISP Shift Register)
Verify
(ISP Shift Register)
Instruction Code
01001
01010
01011
10000
01100
Description
Enables the Erase, Program, and Verify commands. Using the
Enable instruction before the Erase, Program, and Verify
instructions allows the user to specify the outputs of the device
using the JTAG Boundary-Scan Sample/Preload command.
Erases the entire EEPROM array. User can define the outputs
during this operation by using the JTAG Sample/Preload
command.
Programs the data in the ISP Shift Register into the addressed
EEPROM row. The outputs can be defined by using the JTAG
Sample/Preload command.
Disable instruction allows the user to leave ISP mode. It selects
the ISP register to be directly connected between TDO and TDI.
Transfers the data from the addressed row to the ISP Shift
Register. The data can then be shifted out and compared with
the JEDEC file. The user can define the outputs during this
operation.
DS012 (v1.1) March 3, 2000
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